tsunami_cchip.hh revision 1762
112837Sgabeblack@google.com/* 212837Sgabeblack@google.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 312837Sgabeblack@google.com * All rights reserved. 412837Sgabeblack@google.com * 512837Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612837Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712837Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812837Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912837Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012837Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112837Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212837Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312837Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412837Sgabeblack@google.com * this software without specific prior written permission. 1512837Sgabeblack@google.com * 1612837Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712837Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812837Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912837Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012837Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112837Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212837Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312837Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412837Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512837Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612837Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712837Sgabeblack@google.com */ 2812837Sgabeblack@google.com 2912837Sgabeblack@google.com/** @file 3012837Sgabeblack@google.com * Emulation of the Tsunami CChip CSRs 3112837Sgabeblack@google.com */ 3212862Sgabeblack@google.com 3312837Sgabeblack@google.com#ifndef __TSUNAMI_CCHIP_HH__ 3412862Sgabeblack@google.com#define __TSUNAMI_CCHIP_HH__ 3512837Sgabeblack@google.com 3612956Sgabeblack@google.com#include "dev/tsunami.hh" 3712862Sgabeblack@google.com#include "base/range.hh" 3812837Sgabeblack@google.com#include "dev/io_device.hh" 3912956Sgabeblack@google.com 4012837Sgabeblack@google.com/** 4112861Sgabeblack@google.com * Tsunami CChip CSR Emulation. This device includes all the interrupt 4212837Sgabeblack@google.com * handling code for the chipset. 4312949Sgabeblack@google.com */ 4412949Sgabeblack@google.comclass TsunamiCChip : public PioDevice 4512837Sgabeblack@google.com{ 4612837Sgabeblack@google.com private: 4712837Sgabeblack@google.com /** The base address of this device */ 4812837Sgabeblack@google.com Addr addr; 4912837Sgabeblack@google.com 5012837Sgabeblack@google.com /** The size of mappad from the above address */ 5112837Sgabeblack@google.com static const Addr size = 0xfffffff; 5212837Sgabeblack@google.com 5312837Sgabeblack@google.com protected: 5412837Sgabeblack@google.com /** 5512837Sgabeblack@google.com * pointer to the tsunami object. 5612837Sgabeblack@google.com * This is our access to all the other tsunami 5712862Sgabeblack@google.com * devices. 5812862Sgabeblack@google.com */ 5912862Sgabeblack@google.com Tsunami *tsunami; 6012862Sgabeblack@google.com 6112862Sgabeblack@google.com /** 6212949Sgabeblack@google.com * The dims are device interrupt mask registers. 6312949Sgabeblack@google.com * One exists for each CPU, the DRIR X DIM = DIR 6412949Sgabeblack@google.com */ 6512949Sgabeblack@google.com uint64_t dim[Tsunami::Max_CPUs]; 6612949Sgabeblack@google.com 6712949Sgabeblack@google.com /** 6812862Sgabeblack@google.com * The dirs are device interrupt registers. 6912862Sgabeblack@google.com * One exists for each CPU, the DRIR X DIM = DIR 7012862Sgabeblack@google.com */ 7112862Sgabeblack@google.com uint64_t dir[Tsunami::Max_CPUs]; 7212862Sgabeblack@google.com 7312837Sgabeblack@google.com /** 7412837Sgabeblack@google.com * This register contains bits for each PCI interrupt 7512837Sgabeblack@google.com * that can occur. 7612837Sgabeblack@google.com */ 7712837Sgabeblack@google.com uint64_t drir; 7812837Sgabeblack@google.com 7912837Sgabeblack@google.com /** Indicator of which CPUs have an IPI interrupt */ 8012837Sgabeblack@google.com uint64_t ipint; 8112837Sgabeblack@google.com 8212837Sgabeblack@google.com /** Indicator of which CPUs have an RTC interrupt */ 8312837Sgabeblack@google.com uint64_t itint; 8412837Sgabeblack@google.com 8512837Sgabeblack@google.com public: 8612837Sgabeblack@google.com /** 8712837Sgabeblack@google.com * Initialize the Tsunami CChip by setting all of the 8812837Sgabeblack@google.com * device register to 0. 8912837Sgabeblack@google.com * @param name name of this device. 9012837Sgabeblack@google.com * @param t pointer back to the Tsunami object that we belong to. 9112837Sgabeblack@google.com * @param a address we are mapped at. 9212837Sgabeblack@google.com * @param mmu pointer to the memory controller that sends us events. 9312837Sgabeblack@google.com * @param hier object to store parameters universal the device hierarchy 9412837Sgabeblack@google.com * @param bus The bus that this device is attached to 9512837Sgabeblack@google.com */ 9612837Sgabeblack@google.com TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 9712837Sgabeblack@google.com MemoryController *mmu, HierParams *hier, Bus *bus, 9812837Sgabeblack@google.com Tick pio_latency); 9912837Sgabeblack@google.com 10012837Sgabeblack@google.com /** 10112837Sgabeblack@google.com * Process a read to the CChip. 10212837Sgabeblack@google.com * @param req Contains the address to read from. 10312837Sgabeblack@google.com * @param data A pointer to write the read data to. 10412837Sgabeblack@google.com * @return The fault condition of the access. 10512837Sgabeblack@google.com */ 10612837Sgabeblack@google.com virtual Fault read(MemReqPtr &req, uint8_t *data); 10712837Sgabeblack@google.com 10812837Sgabeblack@google.com 10912837Sgabeblack@google.com /** 11012862Sgabeblack@google.com * Process a write to the CChip. 11112837Sgabeblack@google.com * @param req Contains the address to write to. 11212837Sgabeblack@google.com * @param data The data to write. 11312837Sgabeblack@google.com * @return The fault condition of the access. 11412837Sgabeblack@google.com */ 11512837Sgabeblack@google.com virtual Fault write(MemReqPtr &req, const uint8_t *data); 11612837Sgabeblack@google.com 11712837Sgabeblack@google.com /** 11812837Sgabeblack@google.com * post an RTC interrupt to the CPU 11912837Sgabeblack@google.com */ 12012837Sgabeblack@google.com void postRTC(); 12112837Sgabeblack@google.com 12212837Sgabeblack@google.com /** 12312861Sgabeblack@google.com * post an interrupt to the CPU. 12412861Sgabeblack@google.com * @param interrupt the interrupt number to post (0-64) 12512861Sgabeblack@google.com */ 12612837Sgabeblack@google.com void postDRIR(uint32_t interrupt); 12712837Sgabeblack@google.com 12812837Sgabeblack@google.com /** 12912837Sgabeblack@google.com * clear an interrupt previously posted to the CPU. 13012837Sgabeblack@google.com * @param interrupt the interrupt number to post (0-64) 13112837Sgabeblack@google.com */ 13212837Sgabeblack@google.com void clearDRIR(uint32_t interrupt); 13312837Sgabeblack@google.com 13412837Sgabeblack@google.com /** 13512837Sgabeblack@google.com * post an ipi interrupt to the CPU. 13612837Sgabeblack@google.com * @param ipintr the cpu number to clear(bitvector) 13712837Sgabeblack@google.com */ 13812837Sgabeblack@google.com void clearIPI(uint64_t ipintr); 13912837Sgabeblack@google.com 14012860Sgabeblack@google.com /** 14112860Sgabeblack@google.com * clear a timer interrupt previously posted to the CPU. 14212860Sgabeblack@google.com * @param interrupt the cpu number to clear(bitvector) 14312962Sgabeblack@google.com */ 14412961Sgabeblack@google.com void clearITI(uint64_t itintr); 14512860Sgabeblack@google.com 14612860Sgabeblack@google.com /** 14712860Sgabeblack@google.com * request an interrupt be posted to the CPU. 14812860Sgabeblack@google.com * @param ipreq the cpu number to interrupt(bitvector) 14912860Sgabeblack@google.com */ 15012961Sgabeblack@google.com void reqIPI(uint64_t ipreq); 15112961Sgabeblack@google.com 15212860Sgabeblack@google.com 15312860Sgabeblack@google.com /** 15412860Sgabeblack@google.com * Serialize this object to the given output stream. 15512860Sgabeblack@google.com * @param os The stream to serialize to. 15612860Sgabeblack@google.com */ 15712961Sgabeblack@google.com virtual void serialize(std::ostream &os); 15812961Sgabeblack@google.com 15912962Sgabeblack@google.com /** 16012961Sgabeblack@google.com * Reconstruct the state of this object from a checkpoint. 16112862Sgabeblack@google.com * @param cp The checkpoint use. 16212961Sgabeblack@google.com * @param section The section name of this object 16312961Sgabeblack@google.com */ 16412961Sgabeblack@google.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 16512961Sgabeblack@google.com 16612860Sgabeblack@google.com /** 16712860Sgabeblack@google.com * Return how long this access will take. 16812860Sgabeblack@google.com * @param req the memory request to calcuate 16912860Sgabeblack@google.com * @return Tick when the request is done 17012860Sgabeblack@google.com */ 17112861Sgabeblack@google.com Tick cacheAccess(MemReqPtr &req); 17212861Sgabeblack@google.com}; 17312861Sgabeblack@google.com 17412861Sgabeblack@google.com#endif // __TSUNAMI_CCHIP_HH__ 17512861Sgabeblack@google.com