tsunami_cchip.hh revision 11168
1767SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3767SN/A * All rights reserved. 4767SN/A * 5767SN/A * Redistribution and use in source and binary forms, with or without 6767SN/A * modification, are permitted provided that the following conditions are 7767SN/A * met: redistributions of source code must retain the above copyright 8767SN/A * notice, this list of conditions and the following disclaimer; 9767SN/A * redistributions in binary form must reproduce the above copyright 10767SN/A * notice, this list of conditions and the following disclaimer in the 11767SN/A * documentation and/or other materials provided with the distribution; 12767SN/A * neither the name of the copyright holders nor the names of its 13767SN/A * contributors may be used to endorse or promote products derived from 14767SN/A * this software without specific prior written permission. 15767SN/A * 16767SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17767SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18767SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19767SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20767SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21767SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22767SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23767SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24767SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25767SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26767SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 29767SN/A */ 30767SN/A 311722SN/A/** @file 32798SN/A * Emulation of the Tsunami CChip CSRs 33767SN/A */ 34767SN/A 35767SN/A#ifndef __TSUNAMI_CCHIP_HH__ 36767SN/A#define __TSUNAMI_CCHIP_HH__ 37767SN/A 383540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 39909SN/A#include "dev/io_device.hh" 404762Snate@binkert.org#include "params/TsunamiCChip.hh" 411872SN/A 421722SN/A/** 431722SN/A * Tsunami CChip CSR Emulation. This device includes all the interrupt 441722SN/A * handling code for the chipset. 45767SN/A */ 462523SN/Aclass TsunamiCChip : public BasicPioDevice 47767SN/A{ 48767SN/A protected: 49887SN/A /** 50887SN/A * pointer to the tsunami object. 51887SN/A * This is our access to all the other tsunami 52887SN/A * devices. 53887SN/A */ 54767SN/A Tsunami *tsunami; 55798SN/A 56798SN/A /** 57798SN/A * The dims are device interrupt mask registers. 58798SN/A * One exists for each CPU, the DRIR X DIM = DIR 59798SN/A */ 60767SN/A uint64_t dim[Tsunami::Max_CPUs]; 61798SN/A 62798SN/A /** 63798SN/A * The dirs are device interrupt registers. 64798SN/A * One exists for each CPU, the DRIR X DIM = DIR 65798SN/A */ 66767SN/A uint64_t dir[Tsunami::Max_CPUs]; 67798SN/A 68798SN/A /** 69798SN/A * This register contains bits for each PCI interrupt 70798SN/A * that can occur. 71798SN/A */ 72767SN/A uint64_t drir; 73831SN/A 741290SN/A /** Indicator of which CPUs have an IPI interrupt */ 751290SN/A uint64_t ipint; 76831SN/A 771290SN/A /** Indicator of which CPUs have an RTC interrupt */ 781290SN/A uint64_t itint; 79767SN/A 80767SN/A public: 814762Snate@binkert.org typedef TsunamiCChipParams Params; 82885SN/A /** 83885SN/A * Initialize the Tsunami CChip by setting all of the 84885SN/A * device register to 0. 852523SN/A * @param p params struct 86885SN/A */ 874762Snate@binkert.org TsunamiCChip(const Params *p); 884762Snate@binkert.org 894762Snate@binkert.org const Params * 904762Snate@binkert.org params() const 914762Snate@binkert.org { 924762Snate@binkert.org return dynamic_cast<const Params *>(_params); 934762Snate@binkert.org } 94767SN/A 953349SN/A virtual Tick read(PacketPtr pkt); 96885SN/A 973349SN/A virtual Tick write(PacketPtr pkt); 98767SN/A 99885SN/A /** 100885SN/A * post an RTC interrupt to the CPU 101885SN/A */ 102831SN/A void postRTC(); 103885SN/A 104885SN/A /** 105885SN/A * post an interrupt to the CPU. 106885SN/A * @param interrupt the interrupt number to post (0-64) 107885SN/A */ 108817SN/A void postDRIR(uint32_t interrupt); 109885SN/A 110885SN/A /** 111885SN/A * clear an interrupt previously posted to the CPU. 112885SN/A * @param interrupt the interrupt number to post (0-64) 113885SN/A */ 114817SN/A void clearDRIR(uint32_t interrupt); 115777SN/A 116885SN/A /** 1171290SN/A * post an ipi interrupt to the CPU. 1181290SN/A * @param ipintr the cpu number to clear(bitvector) 1191290SN/A */ 1201290SN/A void clearIPI(uint64_t ipintr); 1211290SN/A 1221290SN/A /** 1231290SN/A * clear a timer interrupt previously posted to the CPU. 1241763SN/A * @param itintr the cpu number to clear(bitvector) 1251290SN/A */ 1261290SN/A void clearITI(uint64_t itintr); 1271290SN/A 1281290SN/A /** 1291290SN/A * request an interrupt be posted to the CPU. 1301290SN/A * @param ipreq the cpu number to interrupt(bitvector) 1311290SN/A */ 1321290SN/A void reqIPI(uint64_t ipreq); 1331290SN/A 13411168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 13511168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 136767SN/A}; 137767SN/A 138767SN/A#endif // __TSUNAMI_CCHIP_HH__ 139