tsunami_cchip.cc revision 909
1360SN/A/* 21458SN/A * Copyright (c) 2004 The Regents of The University of Michigan 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * Redistribution and use in source and binary forms, with or without 6360SN/A * modification, are permitted provided that the following conditions are 7360SN/A * met: redistributions of source code must retain the above copyright 8360SN/A * notice, this list of conditions and the following disclaimer; 9360SN/A * redistributions in binary form must reproduce the above copyright 10360SN/A * notice, this list of conditions and the following disclaimer in the 11360SN/A * documentation and/or other materials provided with the distribution; 12360SN/A * neither the name of the copyright holders nor the names of its 13360SN/A * contributors may be used to endorse or promote products derived from 14360SN/A * this software without specific prior written permission. 15360SN/A * 16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23360SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu/* @file 30360SN/A * Emulation of the Tsunami CChip CSRs 31360SN/A */ 3211793Sbrandon.potter@amd.com 3311793Sbrandon.potter@amd.com#include <deque> 342093SN/A#include <string> 3513479Santhony.gutierrez@amd.com#include <vector> 36360SN/A 37360SN/A#include "base/trace.hh" 3811911SBrandon.Potter@amd.com#include "dev/console.hh" 396712Snate@binkert.org#include "dev/tsunami_cchip.hh" 4013031Sbrandon.potter@amd.com#include "dev/tsunamireg.h" 41360SN/A#include "dev/tsunami.hh" 42360SN/A#include "mem/bus/bus.hh" 437680Sgblack@eecs.umich.edu#include "mem/bus/pio_interface.hh" 442474SN/A#include "mem/bus/pio_interface_impl.hh" 45360SN/A#include "mem/functional_mem/memory_control.hh" 466658Snate@binkert.org#include "cpu/intr_control.hh" 472680Sktlim@umich.edu#include "sim/builder.hh" 4812716Smichael.lebeane@amd.com#include "sim/system.hh" 492474SN/A 5013031Sbrandon.potter@amd.comusing namespace std; 51360SN/A 528229Snate@binkert.orgTsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, 5311794Sbrandon.potter@amd.com MemoryController *mmu, HierParams *hier, Bus* bus) 5411794Sbrandon.potter@amd.com : PioDevice(name), addr(a), tsunami(t) 556029Ssteve.reinhardt@amd.com{ 56360SN/A mmu->add_child(this, Range<Addr>(addr, addr + size)); 57360SN/A 582107SN/A for(int i=0; i < Tsunami::Max_CPUs; i++) { 59360SN/A dim[i] = 0; 601450SN/A dir[i] = 0; 6111851Sbrandon.potter@amd.com dirInterrupting[i] = false; 622680Sktlim@umich.edu ipiInterrupting[i] = false; 63360SN/A RTCInterrupting[i] = false; 6411794Sbrandon.potter@amd.com } 652484SN/A 662484SN/A if (bus) { 67360SN/A pioInterface = newPioInterface(name, hier, bus, this, 68360SN/A &TsunamiCChip::cacheAccess); 69360SN/A pioInterface->addAddrRange(addr, addr + size - 1); 701450SN/A } 7111851Sbrandon.potter@amd.com 722680Sktlim@umich.edu drir = 0; 73360SN/A misc = 0; 7411794Sbrandon.potter@amd.com 7511794Sbrandon.potter@amd.com //Put back pointer in tsunami 7611794Sbrandon.potter@amd.com tsunami->cchip = this; 7710831Ssteve.reinhardt@amd.com} 78360SN/A 798149SChris.Emmons@ARM.comFault 808149SChris.Emmons@ARM.comTsunamiCChip::read(MemReqPtr &req, uint8_t *data) 818149SChris.Emmons@ARM.com{ 8211886Sbrandon.potter@amd.com DPRINTF(Tsunami, "read va=%#x size=%d\n", 8311911SBrandon.Potter@amd.com req->vaddr, req->size); 8411886Sbrandon.potter@amd.com 8511911SBrandon.Potter@amd.com Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; 8611911SBrandon.Potter@amd.com ExecContext *xc = req->xc; 8711911SBrandon.Potter@amd.com 8811911SBrandon.Potter@amd.com switch (req->size) { 8911911SBrandon.Potter@amd.com 9011886Sbrandon.potter@amd.com case sizeof(uint64_t): 9111911SBrandon.Potter@amd.com switch(daddr) { 9211911SBrandon.Potter@amd.com case TSDEV_CC_CSR: 9311911SBrandon.Potter@amd.com *(uint64_t*)data = 0x0; 9411911SBrandon.Potter@amd.com return No_Fault; 9511911SBrandon.Potter@amd.com case TSDEV_CC_MTR: 9611911SBrandon.Potter@amd.com panic("TSDEV_CC_MTR not implemeted\n"); 9711911SBrandon.Potter@amd.com return No_Fault; 9811911SBrandon.Potter@amd.com case TSDEV_CC_MISC: 9911911SBrandon.Potter@amd.com *(uint64_t*)data = misc | (xc->cpu_id & 0x3); 10011911SBrandon.Potter@amd.com return No_Fault; 10111911SBrandon.Potter@amd.com case TSDEV_CC_AAR0: 10211911SBrandon.Potter@amd.com case TSDEV_CC_AAR1: 10311911SBrandon.Potter@amd.com case TSDEV_CC_AAR2: 10411911SBrandon.Potter@amd.com case TSDEV_CC_AAR3: 10511911SBrandon.Potter@amd.com *(uint64_t*)data = 0; 10611911SBrandon.Potter@amd.com return No_Fault; 10711911SBrandon.Potter@amd.com case TSDEV_CC_DIM0: 10811911SBrandon.Potter@amd.com *(uint64_t*)data = dim[0]; 10912716Smichael.lebeane@amd.com return No_Fault; 11012716Smichael.lebeane@amd.com case TSDEV_CC_DIM1: 11112716Smichael.lebeane@amd.com *(uint64_t*)data = dim[1]; 11212716Smichael.lebeane@amd.com return No_Fault; 11312716Smichael.lebeane@amd.com case TSDEV_CC_DIM2: 11412716Smichael.lebeane@amd.com *(uint64_t*)data = dim[2]; 11512716Smichael.lebeane@amd.com return No_Fault; 11612716Smichael.lebeane@amd.com case TSDEV_CC_DIM3: 11712716Smichael.lebeane@amd.com *(uint64_t*)data = dim[3]; 11812716Smichael.lebeane@amd.com return No_Fault; 11912716Smichael.lebeane@amd.com case TSDEV_CC_DIR0: 12012716Smichael.lebeane@amd.com *(uint64_t*)data = dir[0]; 12112716Smichael.lebeane@amd.com return No_Fault; 12212716Smichael.lebeane@amd.com case TSDEV_CC_DIR1: 12311911SBrandon.Potter@amd.com *(uint64_t*)data = dir[1]; 12411911SBrandon.Potter@amd.com return No_Fault; 12511911SBrandon.Potter@amd.com case TSDEV_CC_DIR2: 12611911SBrandon.Potter@amd.com *(uint64_t*)data = dir[2]; 12711911SBrandon.Potter@amd.com return No_Fault; 12811911SBrandon.Potter@amd.com case TSDEV_CC_DIR3: 12911911SBrandon.Potter@amd.com *(uint64_t*)data = dir[3]; 13011911SBrandon.Potter@amd.com return No_Fault; 13111911SBrandon.Potter@amd.com case TSDEV_CC_DRIR: 13211911SBrandon.Potter@amd.com *(uint64_t*)data = drir; 13311911SBrandon.Potter@amd.com return No_Fault; 13411911SBrandon.Potter@amd.com case TSDEV_CC_PRBEN: 13511911SBrandon.Potter@amd.com panic("TSDEV_CC_PRBEN not implemented\n"); 13611911SBrandon.Potter@amd.com return No_Fault; 13711911SBrandon.Potter@amd.com case TSDEV_CC_IIC0: 13811911SBrandon.Potter@amd.com case TSDEV_CC_IIC1: 13911911SBrandon.Potter@amd.com case TSDEV_CC_IIC2: 14011911SBrandon.Potter@amd.com case TSDEV_CC_IIC3: 14111911SBrandon.Potter@amd.com panic("TSDEV_CC_IICx not implemented\n"); 14211911SBrandon.Potter@amd.com return No_Fault; 14311911SBrandon.Potter@amd.com case TSDEV_CC_MPR0: 14411911SBrandon.Potter@amd.com case TSDEV_CC_MPR1: 14511911SBrandon.Potter@amd.com case TSDEV_CC_MPR2: 14611911SBrandon.Potter@amd.com case TSDEV_CC_MPR3: 14711911SBrandon.Potter@amd.com panic("TSDEV_CC_MPRx not implemented\n"); 14811911SBrandon.Potter@amd.com return No_Fault; 14911911SBrandon.Potter@amd.com default: 15011911SBrandon.Potter@amd.com panic("default in cchip read reached, accessing 0x%x\n"); 15111911SBrandon.Potter@amd.com } // uint64_t 15211911SBrandon.Potter@amd.com 15311911SBrandon.Potter@amd.com break; 15411911SBrandon.Potter@amd.com case sizeof(uint32_t): 15511911SBrandon.Potter@amd.com case sizeof(uint16_t): 15611911SBrandon.Potter@amd.com case sizeof(uint8_t): 15711911SBrandon.Potter@amd.com default: 15811911SBrandon.Potter@amd.com panic("invalid access size(?) for tsunami register!\n"); 15911911SBrandon.Potter@amd.com } 16011911SBrandon.Potter@amd.com DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 16111911SBrandon.Potter@amd.com 16211911SBrandon.Potter@amd.com return No_Fault; 16311911SBrandon.Potter@amd.com} 16411911SBrandon.Potter@amd.com 16511911SBrandon.Potter@amd.comFault 16611911SBrandon.Potter@amd.comTsunamiCChip::write(MemReqPtr &req, const uint8_t *data) 16711911SBrandon.Potter@amd.com{ 16811911SBrandon.Potter@amd.com DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", 16911911SBrandon.Potter@amd.com req->vaddr, *(uint64_t*)data, req->size); 17011911SBrandon.Potter@amd.com 17111886Sbrandon.potter@amd.com Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; 17211886Sbrandon.potter@amd.com 17311911SBrandon.Potter@amd.com bool supportedWrite = false; 17411911SBrandon.Potter@amd.com uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 17511911SBrandon.Potter@amd.com 17611911SBrandon.Potter@amd.com switch (req->size) { 17711911SBrandon.Potter@amd.com 17811911SBrandon.Potter@amd.com case sizeof(uint64_t): 17911911SBrandon.Potter@amd.com switch(daddr) { 18011911SBrandon.Potter@amd.com case TSDEV_CC_CSR: 18111911SBrandon.Potter@amd.com panic("TSDEV_CC_CSR write\n"); 18211911SBrandon.Potter@amd.com return No_Fault; 18311911SBrandon.Potter@amd.com case TSDEV_CC_MTR: 18411911SBrandon.Potter@amd.com panic("TSDEV_CC_MTR write not implemented\n"); 18511911SBrandon.Potter@amd.com return No_Fault; 18611911SBrandon.Potter@amd.com case TSDEV_CC_MISC: 18711911SBrandon.Potter@amd.com //If it is the 4-7th bit, clear the RTC interrupt 18811911SBrandon.Potter@amd.com uint64_t itintr; 18911911SBrandon.Potter@amd.com if ((itintr = (*(uint64_t*) data) & (0xf<<4))) { 19011911SBrandon.Potter@amd.com //Clear the bits in ITINTR 19111911SBrandon.Potter@amd.com misc &= ~(itintr); 19211911SBrandon.Potter@amd.com for (int i=0; i < size; i++) { 19311886Sbrandon.potter@amd.com if ((itintr & (1 << (i+4))) && RTCInterrupting[i]) { 1948149SChris.Emmons@ARM.com tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 1958149SChris.Emmons@ARM.com RTCInterrupting[i] = false; 19611886Sbrandon.potter@amd.com DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 197360SN/A } 19811911SBrandon.Potter@amd.com } 199360SN/A supportedWrite = true; 200360SN/A } 2011450SN/A //If it is 12th-15th bit, IPI sent to Processor 1 20211911SBrandon.Potter@amd.com uint64_t ipreq; 2036109Ssanchezd@stanford.edu if ((ipreq = (*(uint64_t*) data) & (0xf << 12))) { 20411911SBrandon.Potter@amd.com //Set the bits in IPINTR 2056109Ssanchezd@stanford.edu misc |= (ipreq >> 4); 2066109Ssanchezd@stanford.edu for (int i=0; i < size; i++) { 2076109Ssanchezd@stanford.edu if ((ipreq & (1 << (i + 12)))) { 20811851Sbrandon.potter@amd.com if (!ipiInterrupting[i]) 209360SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ3, 0); 21010318Sandreas.hansson@arm.com ipiInterrupting[i]++; 211360SN/A DPRINTF(IPI, "send cpu=%d pending=%d from=%d\n", i, 212360SN/A ipiInterrupting[i], req->cpu_num); 213360SN/A } 2141450SN/A } 21511851Sbrandon.potter@amd.com supportedWrite = true; 216360SN/A } 217360SN/A //If it is bits 8-11, then clearing IPI's 2186701Sgblack@eecs.umich.edu uint64_t ipintr; 2196701Sgblack@eecs.umich.edu if ((ipintr = (*(uint64_t*) data) & (0xf << 8))) { 2205748SSteve.Reinhardt@amd.com //Clear the bits in IPINTR 22111905SBrandon.Potter@amd.com misc &= ~(ipintr); 22211905SBrandon.Potter@amd.com for (int i=0; i < size; i++) { 22311905SBrandon.Potter@amd.com if ((ipintr & (1 << (i + 8))) && ipiInterrupting[i]) { 2245748SSteve.Reinhardt@amd.com if (!(--ipiInterrupting[i])) 2255748SSteve.Reinhardt@amd.com tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ3, 0); 2265748SSteve.Reinhardt@amd.com DPRINTF(IPI, "clearing cpu=%d pending=%d from=%d\n", i, 22711905SBrandon.Potter@amd.com ipiInterrupting[i] + 1, req->cpu_num); 2285748SSteve.Reinhardt@amd.com } 22911905SBrandon.Potter@amd.com } 2305748SSteve.Reinhardt@amd.com supportedWrite = true; 23111905SBrandon.Potter@amd.com } 23211905SBrandon.Potter@amd.com 23310318Sandreas.hansson@arm.com // ignore NXMs 2345748SSteve.Reinhardt@amd.com if (*(uint64_t*)data & 0x10000000) 23510318Sandreas.hansson@arm.com supportedWrite = true; 2366687Stjones1@inf.ed.ac.uk 2376687Stjones1@inf.ed.ac.uk if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n"); 2386687Stjones1@inf.ed.ac.uk return No_Fault; 23911905SBrandon.Potter@amd.com case TSDEV_CC_AAR0: 2408852Sandreas.hansson@arm.com case TSDEV_CC_AAR1: 2416687Stjones1@inf.ed.ac.uk case TSDEV_CC_AAR2: 2426687Stjones1@inf.ed.ac.uk case TSDEV_CC_AAR3: 24310318Sandreas.hansson@arm.com panic("TSDEV_CC_AARx write not implemeted\n"); 2446687Stjones1@inf.ed.ac.uk return No_Fault; 2458852Sandreas.hansson@arm.com case TSDEV_CC_DIM0: 24610318Sandreas.hansson@arm.com case TSDEV_CC_DIM1: 2476687Stjones1@inf.ed.ac.uk case TSDEV_CC_DIM2: 24811906SBrandon.Potter@amd.com case TSDEV_CC_DIM3: 24910318Sandreas.hansson@arm.com int number; 2508852Sandreas.hansson@arm.com if(daddr == TSDEV_CC_DIM0) 2516687Stjones1@inf.ed.ac.uk number = 0; 2526687Stjones1@inf.ed.ac.uk else if(daddr == TSDEV_CC_DIM1) 2532474SN/A number = 1; 2541450SN/A else if(daddr == TSDEV_CC_DIM2) 2555748SSteve.Reinhardt@amd.com number = 2; 25611905SBrandon.Potter@amd.com else 25711380Salexandru.dutu@amd.com number = 3; 25811905SBrandon.Potter@amd.com 25911905SBrandon.Potter@amd.com uint64_t bitvector; 260360SN/A uint64_t olddim; 261360SN/A uint64_t olddir; 26211886Sbrandon.potter@amd.com 26311886Sbrandon.potter@amd.com olddim = dim[number]; 26411886Sbrandon.potter@amd.com olddir = dir[number]; 26511886Sbrandon.potter@amd.com dim[number] = *(uint64_t*)data; 26611886Sbrandon.potter@amd.com dir[number] = dim[number] & drir; 26711886Sbrandon.potter@amd.com for(int x = 0; x < 64; x++) 26811886Sbrandon.potter@amd.com { 26911886Sbrandon.potter@amd.com bitvector = (uint64_t)1 << x; 27011886Sbrandon.potter@amd.com // Figure out which bits have changed 27111886Sbrandon.potter@amd.com if ((dim[number] & bitvector) != (olddim & bitvector)) 272360SN/A { 2731450SN/A // The bit is now set and it wasn't before (set) 27411851Sbrandon.potter@amd.com if((dim[number] & bitvector) && (dir[number] & bitvector)) 275360SN/A { 2766701Sgblack@eecs.umich.edu tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 27710931Sbrandon.potter@amd.com DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 27810931Sbrandon.potter@amd.com } 27911856Sbrandon.potter@amd.com else if ((olddir & bitvector) && 280360SN/A !(dir[number] & bitvector)) 281360SN/A { 282360SN/A // The bit was set and now its now clear and 2831450SN/A // we were interrupting on that bit before 28411851Sbrandon.potter@amd.com tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 285360SN/A DPRINTF(Tsunami, "dim write resulting in clear" 2866701Sgblack@eecs.umich.edu "dir interrupt to cpu 0\n"); 28710931Sbrandon.potter@amd.com 28811906SBrandon.Potter@amd.com } 2896701Sgblack@eecs.umich.edu 29011856Sbrandon.potter@amd.com 29111856Sbrandon.potter@amd.com } 29211856Sbrandon.potter@amd.com } 29311856Sbrandon.potter@amd.com return No_Fault; 29411856Sbrandon.potter@amd.com case TSDEV_CC_DIR0: 29511856Sbrandon.potter@amd.com case TSDEV_CC_DIR1: 29611906SBrandon.Potter@amd.com case TSDEV_CC_DIR2: 29710931Sbrandon.potter@amd.com case TSDEV_CC_DIR3: 298360SN/A panic("TSDEV_CC_DIR write not implemented\n"); 29911684Snderumigny@gmail.com case TSDEV_CC_DRIR: 3008706Sandreas.hansson@arm.com panic("TSDEV_CC_DRIR write not implemented\n"); 301360SN/A case TSDEV_CC_PRBEN: 3021458SN/A panic("TSDEV_CC_PRBEN write not implemented\n"); 303360SN/A case TSDEV_CC_IIC0: 304360SN/A case TSDEV_CC_IIC1: 3051450SN/A case TSDEV_CC_IIC2: 30611851Sbrandon.potter@amd.com case TSDEV_CC_IIC3: 307360SN/A panic("TSDEV_CC_IICx write not implemented\n"); 3086701Sgblack@eecs.umich.edu case TSDEV_CC_MPR0: 30910931Sbrandon.potter@amd.com case TSDEV_CC_MPR1: 31011906SBrandon.Potter@amd.com case TSDEV_CC_MPR2: 3116701Sgblack@eecs.umich.edu case TSDEV_CC_MPR3: 31211856Sbrandon.potter@amd.com panic("TSDEV_CC_MPRx write not implemented\n"); 31311856Sbrandon.potter@amd.com default: 31411856Sbrandon.potter@amd.com panic("default in cchip read reached, accessing 0x%x\n"); 31511856Sbrandon.potter@amd.com } 31611856Sbrandon.potter@amd.com 31711856Sbrandon.potter@amd.com break; 31811906SBrandon.Potter@amd.com case sizeof(uint32_t): 3198706Sandreas.hansson@arm.com case sizeof(uint16_t): 320360SN/A case sizeof(uint8_t): 32110931Sbrandon.potter@amd.com default: 322360SN/A panic("invalid access size(?) for tsunami register!\n"); 32310931Sbrandon.potter@amd.com } 324360SN/A 3251458SN/A DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 326360SN/A 327360SN/A return No_Fault; 328360SN/A} 3291450SN/A 33011851Sbrandon.potter@amd.comvoid 331360SN/ATsunamiCChip::postRTC() 3326701Sgblack@eecs.umich.edu{ 33310931Sbrandon.potter@amd.com int size = tsunami->intrctrl->cpu->system->execContexts.size(); 3346701Sgblack@eecs.umich.edu 3356701Sgblack@eecs.umich.edu for (int i = 0; i < size; i++) { 336360SN/A if (!RTCInterrupting[i]) { 33711856Sbrandon.potter@amd.com misc |= 16 << i; 33811856Sbrandon.potter@amd.com RTCInterrupting[i] = true; 33910931Sbrandon.potter@amd.com tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 34011856Sbrandon.potter@amd.com DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); 34110931Sbrandon.potter@amd.com } 34210931Sbrandon.potter@amd.com } 343360SN/A 3441458SN/A} 345360SN/A 346360SN/Avoid 347360SN/ATsunamiCChip::postDRIR(uint32_t interrupt) 3481450SN/A{ 34911851Sbrandon.potter@amd.com uint64_t bitvector = (uint64_t)0x1 << interrupt; 3504118Sgblack@eecs.umich.edu drir |= bitvector; 3516701Sgblack@eecs.umich.edu uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 35210931Sbrandon.potter@amd.com for(int i=0; i < size; i++) { 3536701Sgblack@eecs.umich.edu dir[i] = dim[i] & drir; 3546701Sgblack@eecs.umich.edu if (dim[i] & bitvector) { 3556701Sgblack@eecs.umich.edu tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 3566701Sgblack@eecs.umich.edu DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 3574118Sgblack@eecs.umich.edu "interrupt %d\n",i, interrupt); 35811856Sbrandon.potter@amd.com } 35911856Sbrandon.potter@amd.com } 36010931Sbrandon.potter@amd.com} 36111856Sbrandon.potter@amd.com 36210931Sbrandon.potter@amd.comvoid 3634118Sgblack@eecs.umich.eduTsunamiCChip::clearDRIR(uint32_t interrupt) 3644118Sgblack@eecs.umich.edu{ 36510931Sbrandon.potter@amd.com uint64_t bitvector = (uint64_t)0x1 << interrupt; 3664118Sgblack@eecs.umich.edu uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 3674118Sgblack@eecs.umich.edu if (drir & bitvector) 36811379Sbrandon.potter@amd.com { 3694118Sgblack@eecs.umich.edu drir &= ~bitvector; 37011379Sbrandon.potter@amd.com for(int i=0; i < size; i++) { 37111379Sbrandon.potter@amd.com if (dir[i] & bitvector) { 37211379Sbrandon.potter@amd.com tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 37311379Sbrandon.potter@amd.com DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 37411379Sbrandon.potter@amd.com "interrupt %d\n",i, interrupt); 3754118Sgblack@eecs.umich.edu 3764118Sgblack@eecs.umich.edu } 3774118Sgblack@eecs.umich.edu dir[i] = dim[i] & drir; 3784118Sgblack@eecs.umich.edu } 37911851Sbrandon.potter@amd.com } 380360SN/A else 38111383Sbrandon.potter@amd.com DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 38211383Sbrandon.potter@amd.com} 38311383Sbrandon.potter@amd.com 3841458SN/ATick 385360SN/ATsunamiCChip::cacheAccess(MemReqPtr &req) 386360SN/A{ 387360SN/A return curTick + 1000; 388360SN/A} 389360SN/A 3901450SN/A 39111851Sbrandon.potter@amd.comvoid 392360SN/ATsunamiCChip::serialize(std::ostream &os) 3936701Sgblack@eecs.umich.edu{ 39411906SBrandon.Potter@amd.com SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 3956701Sgblack@eecs.umich.edu SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 39611906SBrandon.Potter@amd.com SERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs); 397360SN/A SERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs); 398360SN/A SERIALIZE_SCALAR(drir); 399360SN/A SERIALIZE_SCALAR(misc); 4008706Sandreas.hansson@arm.com SERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs); 401360SN/A} 4021458SN/A 403360SN/Avoid 404360SN/ATsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 4051450SN/A{ 40611851Sbrandon.potter@amd.com UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 4075513SMichael.Adler@intel.com UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 4085513SMichael.Adler@intel.com UNSERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs); 4096731Svince@csl.cornell.edu UNSERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs); 41011906SBrandon.Potter@amd.com UNSERIALIZE_SCALAR(drir); 4116701Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(misc); 41211906SBrandon.Potter@amd.com UNSERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs); 4135513SMichael.Adler@intel.com} 4145513SMichael.Adler@intel.com 4155513SMichael.Adler@intel.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 4165513SMichael.Adler@intel.com 4175513SMichael.Adler@intel.com SimObjectParam<Tsunami *> tsunami; 4185513SMichael.Adler@intel.com SimObjectParam<MemoryController *> mmu; 4195513SMichael.Adler@intel.com Param<Addr> addr; 4205513SMichael.Adler@intel.com SimObjectParam<Bus*> io_bus; 4215513SMichael.Adler@intel.com SimObjectParam<HierParams *> hier; 4225513SMichael.Adler@intel.com 42310955Sdavid.hashe@amd.comEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 42411856Sbrandon.potter@amd.com 4255513SMichael.Adler@intel.comBEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 42610955Sdavid.hashe@amd.com 4275513SMichael.Adler@intel.com INIT_PARAM(tsunami, "Tsunami"), 4285513SMichael.Adler@intel.com INIT_PARAM(mmu, "Memory Controller"), 4295513SMichael.Adler@intel.com INIT_PARAM(addr, "Device Address"), 4305513SMichael.Adler@intel.com INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), 4318706Sandreas.hansson@arm.com INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 4325513SMichael.Adler@intel.com 4335513SMichael.Adler@intel.comEND_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 4345513SMichael.Adler@intel.com 4355513SMichael.Adler@intel.comCREATE_SIM_OBJECT(TsunamiCChip) 43610203SAli.Saidi@ARM.com{ 43711851Sbrandon.potter@amd.com return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus); 43811851Sbrandon.potter@amd.com} 43910203SAli.Saidi@ARM.com 44010203SAli.Saidi@ARM.comREGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 44110203SAli.Saidi@ARM.com