tsunami_cchip.cc revision 831
12817Sksewell@umich.edu/* $Id$ */ 29426SAndreas.Sandberg@ARM.com 39920Syasuko.eckert@amd.com/* @file 48733Sgeoffrey.blake@arm.com * Emulation of the Tsunami CChip CSRs 58733Sgeoffrey.blake@arm.com */ 68733Sgeoffrey.blake@arm.com 78733Sgeoffrey.blake@arm.com#include <deque> 88733Sgeoffrey.blake@arm.com#include <string> 98733Sgeoffrey.blake@arm.com#include <vector> 108733Sgeoffrey.blake@arm.com 118733Sgeoffrey.blake@arm.com#include "base/trace.hh" 128733Sgeoffrey.blake@arm.com#include "cpu/exec_context.hh" 138733Sgeoffrey.blake@arm.com#include "dev/console.hh" 148733Sgeoffrey.blake@arm.com#include "dev/tsunami_cchip.hh" 152817Sksewell@umich.edu#include "dev/tsunamireg.h" 162817Sksewell@umich.edu#include "dev/tsunami.hh" 172817Sksewell@umich.edu#include "cpu/intr_control.hh" 182817Sksewell@umich.edu#include "mem/functional_mem/memory_control.hh" 192817Sksewell@umich.edu#include "sim/builder.hh" 202817Sksewell@umich.edu#include "sim/system.hh" 212817Sksewell@umich.edu 222817Sksewell@umich.eduusing namespace std; 232817Sksewell@umich.edu 242817Sksewell@umich.eduTsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, 252817Sksewell@umich.edu MemoryController *mmu) 262817Sksewell@umich.edu : FunctionalMemory(name), addr(a), tsunami(t) 272817Sksewell@umich.edu{ 282817Sksewell@umich.edu mmu->add_child(this, Range<Addr>(addr, addr + size)); 292817Sksewell@umich.edu 302817Sksewell@umich.edu for(int i=0; i < Tsunami::Max_CPUs; i++) { 312817Sksewell@umich.edu dim[i] = 0; 322817Sksewell@umich.edu dir[i] = 0; 332817Sksewell@umich.edu dirInterrupting[i] = false; 342817Sksewell@umich.edu ipiInterrupting[i] = false; 352817Sksewell@umich.edu RTCInterrupting[i] = false; 362817Sksewell@umich.edu } 372817Sksewell@umich.edu 382817Sksewell@umich.edu drir = 0; 392817Sksewell@umich.edu misc = 0; 402817Sksewell@umich.edu 412817Sksewell@umich.edu //Put back pointer in tsunami 422817Sksewell@umich.edu tsunami->cchip = this; 432817Sksewell@umich.edu} 442817Sksewell@umich.edu 452817Sksewell@umich.eduFault 462817Sksewell@umich.eduTsunamiCChip::read(MemReqPtr &req, uint8_t *data) 476658Snate@binkert.org{ 488229Snate@binkert.org DPRINTF(Tsunami, "read va=%#x size=%d\n", 492935Sksewell@umich.edu req->vaddr, req->size); 502817Sksewell@umich.edu 512834Sksewell@umich.edu Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; 522834Sksewell@umich.edu ExecContext *xc = req->xc; 532834Sksewell@umich.edu 548902Sandreas.hansson@arm.com switch (req->size) { 552834Sksewell@umich.edu 562817Sksewell@umich.edu case sizeof(uint64_t): 572817Sksewell@umich.edu switch(daddr) { 582817Sksewell@umich.edu case TSDEV_CC_CSR: 592817Sksewell@umich.edu *(uint64_t*)data = 0x0; 602817Sksewell@umich.edu return No_Fault; 612817Sksewell@umich.edu case TSDEV_CC_MTR: 622817Sksewell@umich.edu panic("TSDEV_CC_MTR not implemeted\n"); 632817Sksewell@umich.edu return No_Fault; 642817Sksewell@umich.edu case TSDEV_CC_MISC: 652817Sksewell@umich.edu *(uint64_t*)data = misc | (xc->cpu_id & 0x3); 662817Sksewell@umich.edu return No_Fault; 672817Sksewell@umich.edu case TSDEV_CC_AAR0: 682817Sksewell@umich.edu case TSDEV_CC_AAR1: 692817Sksewell@umich.edu case TSDEV_CC_AAR2: 702817Sksewell@umich.edu case TSDEV_CC_AAR3: 712817Sksewell@umich.edu panic("TSDEV_CC_AARx not implemeted\n"); 722817Sksewell@umich.edu return No_Fault; 732817Sksewell@umich.edu case TSDEV_CC_DIM0: 742817Sksewell@umich.edu *(uint64_t*)data = dim[0]; 752817Sksewell@umich.edu return No_Fault; 762817Sksewell@umich.edu case TSDEV_CC_DIM1: 772817Sksewell@umich.edu *(uint64_t*)data = dim[1]; 782817Sksewell@umich.edu return No_Fault; 792817Sksewell@umich.edu case TSDEV_CC_DIM2: 802817Sksewell@umich.edu *(uint64_t*)data = dim[2]; 813784Sgblack@eecs.umich.edu return No_Fault; 826022Sgblack@eecs.umich.edu case TSDEV_CC_DIM3: 833784Sgblack@eecs.umich.edu *(uint64_t*)data = dim[3]; 843784Sgblack@eecs.umich.edu return No_Fault; 856022Sgblack@eecs.umich.edu case TSDEV_CC_DIR0: 863784Sgblack@eecs.umich.edu *(uint64_t*)data = dir[0]; 878887Sgeoffrey.blake@arm.com return No_Fault; 888733Sgeoffrey.blake@arm.com case TSDEV_CC_DIR1: 899023Sgblack@eecs.umich.edu *(uint64_t*)data = dir[1]; 909023Sgblack@eecs.umich.edu return No_Fault; 919023Sgblack@eecs.umich.edu case TSDEV_CC_DIR2: 929023Sgblack@eecs.umich.edu *(uint64_t*)data = dir[2]; 939023Sgblack@eecs.umich.edu return No_Fault; 948541Sgblack@eecs.umich.edu case TSDEV_CC_DIR3: 952817Sksewell@umich.edu *(uint64_t*)data = dir[3]; 962817Sksewell@umich.edu return No_Fault; 972817Sksewell@umich.edu case TSDEV_CC_DRIR: 982817Sksewell@umich.edu *(uint64_t*)data = drir; 9910110Sandreas.hansson@arm.com return No_Fault; 1002817Sksewell@umich.edu case TSDEV_CC_PRBEN: 10110190Sakash.bagdia@arm.com panic("TSDEV_CC_PRBEN not implemented\n"); 10210190Sakash.bagdia@arm.com return No_Fault; 10310190Sakash.bagdia@arm.com case TSDEV_CC_IIC0: 10411005Sandreas.sandberg@arm.com case TSDEV_CC_IIC1: 1055714Shsul@eecs.umich.edu case TSDEV_CC_IIC2: 1065714Shsul@eecs.umich.edu case TSDEV_CC_IIC3: 1075714Shsul@eecs.umich.edu panic("TSDEV_CC_IICx not implemented\n"); 1085715Shsul@eecs.umich.edu return No_Fault; 10910110Sandreas.hansson@arm.com case TSDEV_CC_MPR0: 1105715Shsul@eecs.umich.edu case TSDEV_CC_MPR1: 1115715Shsul@eecs.umich.edu case TSDEV_CC_MPR2: 1122817Sksewell@umich.edu case TSDEV_CC_MPR3: 1132817Sksewell@umich.edu panic("TSDEV_CC_MPRx not implemented\n"); 1142817Sksewell@umich.edu return No_Fault; 1152817Sksewell@umich.edu default: 1163548Sgblack@eecs.umich.edu panic("default in cchip read reached, accessing 0x%x\n"); 1172817Sksewell@umich.edu } // uint64_t 1182817Sksewell@umich.edu 1198541Sgblack@eecs.umich.edu break; 1208541Sgblack@eecs.umich.edu case sizeof(uint32_t): 1218754Sgblack@eecs.umich.edu case sizeof(uint16_t): 12211886Sbrandon.potter@amd.com case sizeof(uint8_t): 12311886Sbrandon.potter@amd.com default: 1248852Sandreas.hansson@arm.com panic("invalid access size(?) for tsunami register!\n"); 1252817Sksewell@umich.edu } 1268852Sandreas.hansson@arm.com DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 1273675Sktlim@umich.edu 1288706Sandreas.hansson@arm.com return No_Fault; 1298706Sandreas.hansson@arm.com} 1308799Sgblack@eecs.umich.edu 1318852Sandreas.hansson@arm.comFault 1328706Sandreas.hansson@arm.comTsunamiCChip::write(MemReqPtr &req, const uint8_t *data) 1332817Sksewell@umich.edu{ 1342817Sksewell@umich.edu DPRINTF(Tsunami, "write - va=%#x size=%d \n", 1352817Sksewell@umich.edu req->vaddr, req->size); 1362817Sksewell@umich.edu 1372817Sksewell@umich.edu Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; 1382817Sksewell@umich.edu 1392817Sksewell@umich.edu bool supportedWrite = false; 1402817Sksewell@umich.edu uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 14110407Smitch.hayenga@arm.com 14210407Smitch.hayenga@arm.com switch (req->size) { 1432817Sksewell@umich.edu 1442817Sksewell@umich.edu case sizeof(uint64_t): 14510407Smitch.hayenga@arm.com switch(daddr) { 1462817Sksewell@umich.edu case TSDEV_CC_CSR: 1472817Sksewell@umich.edu panic("TSDEV_CC_CSR write\n"); 14810407Smitch.hayenga@arm.com return No_Fault; 1492817Sksewell@umich.edu case TSDEV_CC_MTR: 1502817Sksewell@umich.edu panic("TSDEV_CC_MTR write not implemented\n"); 1512817Sksewell@umich.edu return No_Fault; 1522817Sksewell@umich.edu case TSDEV_CC_MISC: 1532817Sksewell@umich.edu //If it is the 4-7th bit, clear the RTC interrupt 1548777Sgblack@eecs.umich.edu uint64_t itintr; 1552817Sksewell@umich.edu if ((itintr = (*(uint64_t*) data) & (0xf<<4))) { 1562817Sksewell@umich.edu //Clear the bits in ITINTR 1572817Sksewell@umich.edu misc &= ~(itintr); 1582817Sksewell@umich.edu for (int i=0; i < size; i++) { 1592817Sksewell@umich.edu if ((itintr & (1 << (i+4))) && RTCInterrupting[i]) { 1602817Sksewell@umich.edu tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 1612817Sksewell@umich.edu RTCInterrupting[i] = false; 1622817Sksewell@umich.edu DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 1632817Sksewell@umich.edu } 1642817Sksewell@umich.edu } 1652817Sksewell@umich.edu supportedWrite = true; 1662817Sksewell@umich.edu } 1672817Sksewell@umich.edu //If it is 12th-15th bit, IPI sent to Processor 1 1682817Sksewell@umich.edu uint64_t ipreq; 1692817Sksewell@umich.edu if ((ipreq = (*(uint64_t*) data) & (0xf << 12))) { 1702817Sksewell@umich.edu //Set the bits in IPINTR 1712817Sksewell@umich.edu misc |= (ipreq >> 4); 1722817Sksewell@umich.edu for (int i=0; i < size; i++) { 1732817Sksewell@umich.edu if ((ipreq & (1 << (i + 12)))) { 1742817Sksewell@umich.edu if (!ipiInterrupting[i]) 1752817Sksewell@umich.edu tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ3, 0); 1762817Sksewell@umich.edu ipiInterrupting[i]++; 1772817Sksewell@umich.edu DPRINTF(IPI, "send cpu=%d pending=%d from=%d\n", i, 1789426SAndreas.Sandberg@ARM.com ipiInterrupting[i], req->cpu_num); 1799426SAndreas.Sandberg@ARM.com } 1809426SAndreas.Sandberg@ARM.com } 1812817Sksewell@umich.edu supportedWrite = true; 1829426SAndreas.Sandberg@ARM.com } 1839426SAndreas.Sandberg@ARM.com //If it is bits 8-11, then clearing IPI's 1849426SAndreas.Sandberg@ARM.com uint64_t ipintr; 1852817Sksewell@umich.edu if ((ipintr = (*(uint64_t*) data) & (0xf << 8))) { 1869426SAndreas.Sandberg@ARM.com //Clear the bits in IPINTR 1879426SAndreas.Sandberg@ARM.com misc &= ~(ipintr); 1889426SAndreas.Sandberg@ARM.com for (int i=0; i < size; i++) { 1892817Sksewell@umich.edu if ((ipintr & (1 << (i + 8))) && ipiInterrupting[i]) { 1909920Syasuko.eckert@amd.com if (!(--ipiInterrupting[i])) 1919920Syasuko.eckert@amd.com tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ3, 0); 1929920Syasuko.eckert@amd.com DPRINTF(IPI, "clearing cpu=%d pending=%d from=%d\n", i, 1939920Syasuko.eckert@amd.com ipiInterrupting[i] + 1, req->cpu_num); 1942817Sksewell@umich.edu } 1959426SAndreas.Sandberg@ARM.com } 1969426SAndreas.Sandberg@ARM.com supportedWrite = true; 1979426SAndreas.Sandberg@ARM.com } 1982817Sksewell@umich.edu if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n"); 1999426SAndreas.Sandberg@ARM.com return No_Fault; 2009426SAndreas.Sandberg@ARM.com case TSDEV_CC_AAR0: 2019426SAndreas.Sandberg@ARM.com case TSDEV_CC_AAR1: 2022817Sksewell@umich.edu case TSDEV_CC_AAR2: 2039426SAndreas.Sandberg@ARM.com case TSDEV_CC_AAR3: 2049426SAndreas.Sandberg@ARM.com panic("TSDEV_CC_AARx write not implemeted\n"); 2059426SAndreas.Sandberg@ARM.com return No_Fault; 2062817Sksewell@umich.edu case TSDEV_CC_DIM0: 2079920Syasuko.eckert@amd.com case TSDEV_CC_DIM1: 2089920Syasuko.eckert@amd.com case TSDEV_CC_DIM2: 2099920Syasuko.eckert@amd.com case TSDEV_CC_DIM3: 2109920Syasuko.eckert@amd.com int number; 2117720Sgblack@eecs.umich.edu if(daddr == TSDEV_CC_DIM0) 2127720Sgblack@eecs.umich.edu number = 0; 2137720Sgblack@eecs.umich.edu else if(daddr == TSDEV_CC_DIM1) 2147720Sgblack@eecs.umich.edu number = 1; 2157720Sgblack@eecs.umich.edu else if(daddr == TSDEV_CC_DIM2) 2167720Sgblack@eecs.umich.edu number = 2; 2177720Sgblack@eecs.umich.edu else 2188733Sgeoffrey.blake@arm.com number = 3; 2198733Sgeoffrey.blake@arm.com 2202817Sksewell@umich.edu uint64_t bitvector; 2217720Sgblack@eecs.umich.edu uint64_t olddim; 2227720Sgblack@eecs.umich.edu uint64_t olddir; 2232817Sksewell@umich.edu 2242817Sksewell@umich.edu olddim = dim[number]; 2257720Sgblack@eecs.umich.edu olddir = dir[number]; 2267720Sgblack@eecs.umich.edu dim[number] = *(uint64_t*)data; 2272817Sksewell@umich.edu dir[number] = dim[number] & drir; 2287720Sgblack@eecs.umich.edu for(int x = 0; x < 64; x++) 2297720Sgblack@eecs.umich.edu { 2307720Sgblack@eecs.umich.edu bitvector = (uint64_t)1 << x; 2315259Sksewell@umich.edu // Figure out which bits have changed 2322817Sksewell@umich.edu if ((dim[number] & bitvector) != (olddim & bitvector)) 23310698Sandreas.hansson@arm.com { 2345715Shsul@eecs.umich.edu // The bit is now set and it wasn't before (set) 2354172Ssaidi@eecs.umich.edu if((dim[number] & bitvector) && (dir[number] & bitvector)) 2364172Ssaidi@eecs.umich.edu { 2374172Ssaidi@eecs.umich.edu tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 2382817Sksewell@umich.edu DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 2395715Shsul@eecs.umich.edu } 2402817Sksewell@umich.edu else if ((olddir & bitvector) && 2412817Sksewell@umich.edu !(dir[number] & bitvector)) 2424172Ssaidi@eecs.umich.edu { 2432817Sksewell@umich.edu // The bit was set and now its now clear and 2442817Sksewell@umich.edu // we were interrupting on that bit before 2452817Sksewell@umich.edu tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 2464172Ssaidi@eecs.umich.edu DPRINTF(Tsunami, "dim write resulting in clear" 2472817Sksewell@umich.edu "dir interrupt to cpu 0\n"); 2486313Sgblack@eecs.umich.edu 2496313Sgblack@eecs.umich.edu } 2509920Syasuko.eckert@amd.com 25110033SAli.Saidi@ARM.com 2526313Sgblack@eecs.umich.edu } 2532817Sksewell@umich.edu } 2542817Sksewell@umich.edu return No_Fault; 2552817Sksewell@umich.edu case TSDEV_CC_DIR0: 2562817Sksewell@umich.edu case TSDEV_CC_DIR1: 2572817Sksewell@umich.edu case TSDEV_CC_DIR2: 2582817Sksewell@umich.edu case TSDEV_CC_DIR3: 2592817Sksewell@umich.edu panic("TSDEV_CC_DIR write not implemented\n"); 2602817Sksewell@umich.edu case TSDEV_CC_DRIR: 2612817Sksewell@umich.edu panic("TSDEV_CC_DRIR write not implemented\n"); 2622817Sksewell@umich.edu case TSDEV_CC_PRBEN: 26311877Sbrandon.potter@amd.com panic("TSDEV_CC_PRBEN write not implemented\n"); 26411877Sbrandon.potter@amd.com case TSDEV_CC_IIC0: 2652817Sksewell@umich.edu case TSDEV_CC_IIC1: 2662817Sksewell@umich.edu case TSDEV_CC_IIC2: 2672817Sksewell@umich.edu case TSDEV_CC_IIC3: 2688777Sgblack@eecs.umich.edu panic("TSDEV_CC_IICx write not implemented\n"); 2695595Sgblack@eecs.umich.edu case TSDEV_CC_MPR0: 2705595Sgblack@eecs.umich.edu case TSDEV_CC_MPR1: 2715595Sgblack@eecs.umich.edu case TSDEV_CC_MPR2: 2725595Sgblack@eecs.umich.edu case TSDEV_CC_MPR3: 2735595Sgblack@eecs.umich.edu panic("TSDEV_CC_MPRx write not implemented\n"); 2749382SAli.Saidi@ARM.com default: 2759382SAli.Saidi@ARM.com panic("default in cchip read reached, accessing 0x%x\n"); 2769382SAli.Saidi@ARM.com } 2779382SAli.Saidi@ARM.com 2789382SAli.Saidi@ARM.com break; 2799382SAli.Saidi@ARM.com case sizeof(uint32_t): 2809382SAli.Saidi@ARM.com case sizeof(uint16_t): 2819382SAli.Saidi@ARM.com case sizeof(uint8_t): 2829382SAli.Saidi@ARM.com default: 2839382SAli.Saidi@ARM.com panic("invalid access size(?) for tsunami register!\n"); 2845595Sgblack@eecs.umich.edu } 2859426SAndreas.Sandberg@ARM.com 2869426SAndreas.Sandberg@ARM.com DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 2879426SAndreas.Sandberg@ARM.com 2889426SAndreas.Sandberg@ARM.com return No_Fault; 2899426SAndreas.Sandberg@ARM.com} 2909426SAndreas.Sandberg@ARM.com 2919426SAndreas.Sandberg@ARM.comvoid 2929426SAndreas.Sandberg@ARM.comTsunamiCChip::postRTC() 2939920Syasuko.eckert@amd.com{ 2949920Syasuko.eckert@amd.com int size = tsunami->intrctrl->cpu->system->execContexts.size(); 2959920Syasuko.eckert@amd.com 2962817Sksewell@umich.edu for (int i = 0; i < size; i++) { 2972817Sksewell@umich.edu if (!RTCInterrupting[i]) { 2982817Sksewell@umich.edu misc |= 16 << i; 299 RTCInterrupting[i] = true; 300 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 301 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); 302 } 303 } 304 305} 306 307void 308TsunamiCChip::postDRIR(uint32_t interrupt) 309{ 310 uint64_t bitvector = (uint64_t)0x1 << interrupt; 311 drir |= bitvector; 312 uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 313 for(int i=0; i < size; i++) { 314 dir[i] = dim[i] & drir; 315 if (dim[i] & bitvector) { 316 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 317 DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 318 "interrupt %d\n",i, interrupt); 319 } 320 } 321} 322 323void 324TsunamiCChip::clearDRIR(uint32_t interrupt) 325{ 326 uint64_t bitvector = (uint64_t)0x1 << interrupt; 327 uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 328 if (drir & bitvector) 329 { 330 drir &= ~bitvector; 331 for(int i=0; i < size; i++) { 332 if (dir[i] & bitvector) { 333 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 334 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 335 "interrupt %d\n",i, interrupt); 336 337 } 338 dir[i] = dim[i] & drir; 339 } 340 } 341 else 342 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 343} 344 345void 346TsunamiCChip::serialize(std::ostream &os) 347{ 348 SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 349 SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 350 SERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs); 351 SERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs); 352 SERIALIZE_SCALAR(drir); 353 SERIALIZE_SCALAR(misc); 354 SERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs); 355} 356 357void 358TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 359{ 360 UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 361 UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 362 UNSERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs); 363 UNSERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs); 364 UNSERIALIZE_SCALAR(drir); 365 UNSERIALIZE_SCALAR(misc); 366 UNSERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs); 367} 368 369BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 370 371 SimObjectParam<Tsunami *> tsunami; 372 SimObjectParam<MemoryController *> mmu; 373 Param<Addr> addr; 374 375END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 376 377BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 378 379 INIT_PARAM(tsunami, "Tsunami"), 380 INIT_PARAM(mmu, "Memory Controller"), 381 INIT_PARAM(addr, "Device Address") 382 383END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 384 385CREATE_SIM_OBJECT(TsunamiCChip) 386{ 387 return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu); 388} 389 390REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 391