tsunami_cchip.cc revision 777
1360SN/A/* $Id$ */ 21458SN/A 3360SN/A/* @file 4360SN/A * Tsunami CChip (processor, memory, or IO) 5360SN/A */ 6360SN/A 7360SN/A#include <deque> 8360SN/A#include <string> 9360SN/A#include <vector> 10360SN/A 11360SN/A#include "base/trace.hh" 12360SN/A#include "cpu/exec_context.hh" 13360SN/A#include "dev/console.hh" 14360SN/A#include "dev/etherdev.hh" 15360SN/A#include "dev/scsi_ctrl.hh" 16360SN/A#include "dev/tlaser_clock.hh" 17360SN/A#include "dev/tsunami_cchip.hh" 18360SN/A#include "dev/tsunamireg.h" 19360SN/A#include "dev/tsunami.hh" 20360SN/A#include "cpu/intr_control.hh" 21360SN/A#include "mem/functional_mem/memory_control.hh" 22360SN/A#include "sim/builder.hh" 23360SN/A#include "sim/system.hh" 24360SN/A 25360SN/Ausing namespace std; 26360SN/A 272665Ssaidi@eecs.umich.eduTsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, 282665Ssaidi@eecs.umich.edu Addr addr, Addr mask, MemoryController *mmu) 292665Ssaidi@eecs.umich.edu : MmapDevice(name, addr, mask, mmu), tsunami(t) 30360SN/A{ 31360SN/A for(int i=0; i < Tsunami::Max_CPUs; i++) { 3211793Sbrandon.potter@amd.com dim[i] = 0; 3311793Sbrandon.potter@amd.com dir[i] = 0; 342093SN/A dirInterrupting[i] = false; 35360SN/A } 36360SN/A 3711911SBrandon.Potter@amd.com drir = 0; 386712Snate@binkert.org misc = 0; 39360SN/A RTCInterrupting = false; 40360SN/A 417680Sgblack@eecs.umich.edu //Put back pointer in tsunami 422474SN/A tsunami->cchip = this; 43360SN/A} 446658Snate@binkert.org 452680Sktlim@umich.eduFault 462474SN/ATsunamiCChip::read(MemReqPtr req, uint8_t *data) 47360SN/A{ 488229Snate@binkert.org DPRINTF(Tsunami, "read va=%#x size=%d\n", 4911794Sbrandon.potter@amd.com req->vaddr, req->size); 5011794Sbrandon.potter@amd.com 516029Ssteve.reinhardt@amd.com Addr daddr = (req->paddr & addr_mask) >> 6; 52360SN/A// ExecContext *xc = req->xc; 53360SN/A// int cpuid = xc->cpu_id; 542107SN/A 55360SN/A switch (req->size) { 561450SN/A 5711851Sbrandon.potter@amd.com case sizeof(uint64_t): 582680Sktlim@umich.edu switch(daddr) { 59360SN/A case TSDEV_CC_CSR: 6011794Sbrandon.potter@amd.com *(uint64_t*)data = 0x0; 612484SN/A return No_Fault; 622484SN/A case TSDEV_CC_MTR: 63360SN/A panic("TSDEV_CC_MTR not implemeted\n"); 64360SN/A return No_Fault; 65360SN/A case TSDEV_CC_MISC: 661450SN/A *(uint64_t*)data = misc; 6711851Sbrandon.potter@amd.com return No_Fault; 682680Sktlim@umich.edu case TSDEV_CC_AAR0: 69360SN/A case TSDEV_CC_AAR1: 7011794Sbrandon.potter@amd.com case TSDEV_CC_AAR2: 7111794Sbrandon.potter@amd.com case TSDEV_CC_AAR3: 7211794Sbrandon.potter@amd.com panic("TSDEV_CC_AARx not implemeted\n"); 7310831Ssteve.reinhardt@amd.com return No_Fault; 74360SN/A case TSDEV_CC_DIM0: 758149SChris.Emmons@ARM.com *(uint64_t*)data = dim[0]; 768149SChris.Emmons@ARM.com return No_Fault; 778149SChris.Emmons@ARM.com case TSDEV_CC_DIM1: 7811886Sbrandon.potter@amd.com *(uint64_t*)data = dim[1]; 7911911SBrandon.Potter@amd.com return No_Fault; 8011886Sbrandon.potter@amd.com case TSDEV_CC_DIM2: 8111911SBrandon.Potter@amd.com *(uint64_t*)data = dim[2]; 8211911SBrandon.Potter@amd.com return No_Fault; 8311911SBrandon.Potter@amd.com case TSDEV_CC_DIM3: 8411911SBrandon.Potter@amd.com *(uint64_t*)data = dim[3]; 8511911SBrandon.Potter@amd.com return No_Fault; 8611886Sbrandon.potter@amd.com case TSDEV_CC_DIR0: 8711911SBrandon.Potter@amd.com *(uint64_t*)data = dir[0]; 8811911SBrandon.Potter@amd.com return No_Fault; 8911911SBrandon.Potter@amd.com case TSDEV_CC_DIR1: 9011911SBrandon.Potter@amd.com *(uint64_t*)data = dir[1]; 9111911SBrandon.Potter@amd.com return No_Fault; 9211911SBrandon.Potter@amd.com case TSDEV_CC_DIR2: 9311911SBrandon.Potter@amd.com *(uint64_t*)data = dir[2]; 9411911SBrandon.Potter@amd.com return No_Fault; 9511911SBrandon.Potter@amd.com case TSDEV_CC_DIR3: 9611911SBrandon.Potter@amd.com *(uint64_t*)data = dir[3]; 9711911SBrandon.Potter@amd.com return No_Fault; 9811911SBrandon.Potter@amd.com case TSDEV_CC_DRIR: 9911911SBrandon.Potter@amd.com *(uint64_t*)data = drir; 10011911SBrandon.Potter@amd.com return No_Fault; 10111911SBrandon.Potter@amd.com case TSDEV_CC_PRBEN: 10211911SBrandon.Potter@amd.com panic("TSDEV_CC_PRBEN not implemented\n"); 10311911SBrandon.Potter@amd.com return No_Fault; 10411911SBrandon.Potter@amd.com case TSDEV_CC_IIC0: 10511911SBrandon.Potter@amd.com case TSDEV_CC_IIC1: 10611911SBrandon.Potter@amd.com case TSDEV_CC_IIC2: 10711911SBrandon.Potter@amd.com case TSDEV_CC_IIC3: 10811911SBrandon.Potter@amd.com panic("TSDEV_CC_IICx not implemented\n"); 10911911SBrandon.Potter@amd.com return No_Fault; 11011911SBrandon.Potter@amd.com case TSDEV_CC_MPR0: 11111911SBrandon.Potter@amd.com case TSDEV_CC_MPR1: 11211911SBrandon.Potter@amd.com case TSDEV_CC_MPR2: 11311911SBrandon.Potter@amd.com case TSDEV_CC_MPR3: 11411911SBrandon.Potter@amd.com panic("TSDEV_CC_MPRx not implemented\n"); 11511911SBrandon.Potter@amd.com return No_Fault; 11611911SBrandon.Potter@amd.com default: 11711911SBrandon.Potter@amd.com panic("default in cchip read reached, accessing 0x%x\n"); 11811911SBrandon.Potter@amd.com } // uint64_t 11911911SBrandon.Potter@amd.com 12011911SBrandon.Potter@amd.com break; 12111911SBrandon.Potter@amd.com case sizeof(uint32_t): 12211911SBrandon.Potter@amd.com case sizeof(uint16_t): 12311911SBrandon.Potter@amd.com case sizeof(uint8_t): 12411911SBrandon.Potter@amd.com default: 12511911SBrandon.Potter@amd.com panic("invalid access size(?) for tsunami register!\n"); 12611911SBrandon.Potter@amd.com } 12711911SBrandon.Potter@amd.com DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 12811911SBrandon.Potter@amd.com 12911911SBrandon.Potter@amd.com return No_Fault; 13011911SBrandon.Potter@amd.com} 13111911SBrandon.Potter@amd.com 13211911SBrandon.Potter@amd.comFault 13311911SBrandon.Potter@amd.comTsunamiCChip::write(MemReqPtr req, const uint8_t *data) 13411911SBrandon.Potter@amd.com{ 13511911SBrandon.Potter@amd.com DPRINTF(Tsunami, "write - va=%#x size=%d \n", 13611911SBrandon.Potter@amd.com req->vaddr, req->size); 13711911SBrandon.Potter@amd.com 13811911SBrandon.Potter@amd.com Addr daddr = (req->paddr & addr_mask) >> 6; 13911911SBrandon.Potter@amd.com 14011911SBrandon.Potter@amd.com switch (req->size) { 14111911SBrandon.Potter@amd.com 14211911SBrandon.Potter@amd.com case sizeof(uint64_t): 14311911SBrandon.Potter@amd.com switch(daddr) { 14411911SBrandon.Potter@amd.com case TSDEV_CC_CSR: 14511911SBrandon.Potter@amd.com panic("TSDEV_CC_CSR write\n"); 14611911SBrandon.Potter@amd.com return No_Fault; 14711911SBrandon.Potter@amd.com case TSDEV_CC_MTR: 14811911SBrandon.Potter@amd.com panic("TSDEV_CC_MTR write not implemented\n"); 14911911SBrandon.Potter@amd.com return No_Fault; 15011911SBrandon.Potter@amd.com case TSDEV_CC_MISC: 15111911SBrandon.Potter@amd.com //If it is the seventh bit, clear the RTC interrupt 15211911SBrandon.Potter@amd.com if ((*(uint64_t*) data) & (1<<4)) { 15311886Sbrandon.potter@amd.com RTCInterrupting = false; 15411886Sbrandon.potter@amd.com tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0); 15511911SBrandon.Potter@amd.com DPRINTF(Tsunami, "clearing rtc interrupt\n"); 15611911SBrandon.Potter@amd.com misc &= ~(1<<4); 15711911SBrandon.Potter@amd.com } else panic("TSDEV_CC_MISC write not implemented\n"); 15811911SBrandon.Potter@amd.com return No_Fault; 15911911SBrandon.Potter@amd.com case TSDEV_CC_AAR0: 16011911SBrandon.Potter@amd.com case TSDEV_CC_AAR1: 16111911SBrandon.Potter@amd.com case TSDEV_CC_AAR2: 16211911SBrandon.Potter@amd.com case TSDEV_CC_AAR3: 16311911SBrandon.Potter@amd.com panic("TSDEV_CC_AARx write not implemeted\n"); 16411911SBrandon.Potter@amd.com return No_Fault; 16511911SBrandon.Potter@amd.com case TSDEV_CC_DIM0: 16611911SBrandon.Potter@amd.com dim[0] = *(uint64_t*)data; 16711911SBrandon.Potter@amd.com if (dim[0] & drir) { 16811911SBrandon.Potter@amd.com dir[0] = dim[0] & drir; 16911911SBrandon.Potter@amd.com if (!dirInterrupting[0]) { 17011911SBrandon.Potter@amd.com dirInterrupting[0] = true; 17111911SBrandon.Potter@amd.com tsunami->intrctrl->post(0, TheISA::INTLEVEL_IRQ1, 0); 17211911SBrandon.Potter@amd.com DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 17311911SBrandon.Potter@amd.com } 17411911SBrandon.Potter@amd.com } 17511886Sbrandon.potter@amd.com return No_Fault; 1768149SChris.Emmons@ARM.com case TSDEV_CC_DIM1: 1778149SChris.Emmons@ARM.com dim[1] = *(uint64_t*)data; 17811886Sbrandon.potter@amd.com if (dim[1] & drir) { 179360SN/A dir[1] = dim[1] & drir; 18011911SBrandon.Potter@amd.com if (!dirInterrupting[1]) { 181360SN/A dirInterrupting[1] = true; 182360SN/A tsunami->intrctrl->post(1, TheISA::INTLEVEL_IRQ1, 0); 1831450SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu 1\n"); 18411911SBrandon.Potter@amd.com } 1856109Ssanchezd@stanford.edu } 18611911SBrandon.Potter@amd.com return No_Fault; 1876109Ssanchezd@stanford.edu case TSDEV_CC_DIM2: 1886109Ssanchezd@stanford.edu dim[2] = *(uint64_t*)data; 1896109Ssanchezd@stanford.edu if (dim[2] & drir) { 19011851Sbrandon.potter@amd.com dir[2] = dim[2] & drir; 191360SN/A if (!dirInterrupting[2]) { 19210318Sandreas.hansson@arm.com dirInterrupting[2] = true; 193360SN/A tsunami->intrctrl->post(2, TheISA::INTLEVEL_IRQ1, 0); 194360SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu 2\n"); 195360SN/A } 1961450SN/A } 19711851Sbrandon.potter@amd.com return No_Fault; 198360SN/A case TSDEV_CC_DIM3: 199360SN/A dim[3] = *(uint64_t*)data; 2006701Sgblack@eecs.umich.edu if ((dim[3] & drir) /*And Not Already Int*/) { 2016701Sgblack@eecs.umich.edu dir[3] = dim[3] & drir; 2025748SSteve.Reinhardt@amd.com if (!dirInterrupting[3]) { 20311905SBrandon.Potter@amd.com dirInterrupting[3] = true; 20411905SBrandon.Potter@amd.com tsunami->intrctrl->post(3, TheISA::INTLEVEL_IRQ1, 0); 20511905SBrandon.Potter@amd.com DPRINTF(Tsunami, "posting dir interrupt to cpu 3\n"); 2065748SSteve.Reinhardt@amd.com } 2075748SSteve.Reinhardt@amd.com } 2085748SSteve.Reinhardt@amd.com return No_Fault; 20911905SBrandon.Potter@amd.com case TSDEV_CC_DIR0: 2105748SSteve.Reinhardt@amd.com case TSDEV_CC_DIR1: 21111905SBrandon.Potter@amd.com case TSDEV_CC_DIR2: 2125748SSteve.Reinhardt@amd.com case TSDEV_CC_DIR3: 21311905SBrandon.Potter@amd.com panic("TSDEV_CC_DIR write not implemented\n"); 21411905SBrandon.Potter@amd.com return No_Fault; 21510318Sandreas.hansson@arm.com case TSDEV_CC_DRIR: 2165748SSteve.Reinhardt@amd.com panic("TSDEV_CC_DRIR write not implemented\n"); 21710318Sandreas.hansson@arm.com return No_Fault; 2186687Stjones1@inf.ed.ac.uk case TSDEV_CC_PRBEN: 2196687Stjones1@inf.ed.ac.uk panic("TSDEV_CC_PRBEN write not implemented\n"); 2206687Stjones1@inf.ed.ac.uk return No_Fault; 22111905SBrandon.Potter@amd.com case TSDEV_CC_IIC0: 2228852Sandreas.hansson@arm.com case TSDEV_CC_IIC1: 2236687Stjones1@inf.ed.ac.uk case TSDEV_CC_IIC2: 2246687Stjones1@inf.ed.ac.uk case TSDEV_CC_IIC3: 22510318Sandreas.hansson@arm.com panic("TSDEV_CC_IICx write not implemented\n"); 2266687Stjones1@inf.ed.ac.uk return No_Fault; 2278852Sandreas.hansson@arm.com case TSDEV_CC_MPR0: 22810318Sandreas.hansson@arm.com case TSDEV_CC_MPR1: 2296687Stjones1@inf.ed.ac.uk case TSDEV_CC_MPR2: 23011906SBrandon.Potter@amd.com case TSDEV_CC_MPR3: 23110318Sandreas.hansson@arm.com panic("TSDEV_CC_MPRx write not implemented\n"); 2328852Sandreas.hansson@arm.com return No_Fault; 2336687Stjones1@inf.ed.ac.uk default: 2346687Stjones1@inf.ed.ac.uk panic("default in cchip read reached, accessing 0x%x\n"); 2352474SN/A } 2361450SN/A 2375748SSteve.Reinhardt@amd.com break; 23811905SBrandon.Potter@amd.com case sizeof(uint32_t): 23911380Salexandru.dutu@amd.com case sizeof(uint16_t): 24011905SBrandon.Potter@amd.com case sizeof(uint8_t): 24111905SBrandon.Potter@amd.com default: 242360SN/A panic("invalid access size(?) for tsunami register!\n"); 243360SN/A } 24411886Sbrandon.potter@amd.com 24511886Sbrandon.potter@amd.com DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 24611886Sbrandon.potter@amd.com 24711886Sbrandon.potter@amd.com return No_Fault; 24811886Sbrandon.potter@amd.com} 24911886Sbrandon.potter@amd.com 25011886Sbrandon.potter@amd.comvoid 25111886Sbrandon.potter@amd.comTsunamiCChip::postDRIR(uint64_t bitvector) 25211886Sbrandon.potter@amd.com{ 25311886Sbrandon.potter@amd.com drir |= bitvector; 254360SN/A for(int i=0; i < Tsunami::Max_CPUs; i++) { 2551450SN/A if (bitvector & dim[i]) { 25611851Sbrandon.potter@amd.com dir[i] |= bitvector; 257360SN/A if (!dirInterrupting[i]) { 2586701Sgblack@eecs.umich.edu dirInterrupting[i] = true; 25910931Sbrandon.potter@amd.com tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, 0); 26010931Sbrandon.potter@amd.com DPRINTF(Tsunami, "posting dir interrupt to cpu %d\n",i); 26111856Sbrandon.potter@amd.com } 262360SN/A } 263360SN/A } 264360SN/A} 2651450SN/A 26611851Sbrandon.potter@amd.comvoid 267360SN/ATsunamiCChip::clearDRIR(uint64_t bitvector) 2686701Sgblack@eecs.umich.edu{ 26910931Sbrandon.potter@amd.com drir &= ~bitvector; 27011906SBrandon.Potter@amd.com for(int i=0; i < Tsunami::Max_CPUs; i++) { 2716701Sgblack@eecs.umich.edu dir[i] &= ~bitvector; 27211856Sbrandon.potter@amd.com if (!dir[i]) { 27311856Sbrandon.potter@amd.com dirInterrupting[i] = false; 27411856Sbrandon.potter@amd.com tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, 0); 27511856Sbrandon.potter@amd.com DPRINTF(Tsunami, "clearing dir interrupt to cpu %d\n", i); 27611856Sbrandon.potter@amd.com 27711856Sbrandon.potter@amd.com } 27811906SBrandon.Potter@amd.com } 27910931Sbrandon.potter@amd.com} 280360SN/A 28111684Snderumigny@gmail.comvoid 2828706Sandreas.hansson@arm.comTsunamiCChip::serialize(std::ostream &os) 283360SN/A{ 2841458SN/A // code should be written 285360SN/A} 286360SN/A 2871450SN/Avoid 28811851Sbrandon.potter@amd.comTsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 289360SN/A{ 2906701Sgblack@eecs.umich.edu //code should be written 29110931Sbrandon.potter@amd.com} 29211906SBrandon.Potter@amd.com 2936701Sgblack@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 29411856Sbrandon.potter@amd.com 29511856Sbrandon.potter@amd.com SimObjectParam<Tsunami *> tsunami; 29611856Sbrandon.potter@amd.com SimObjectParam<MemoryController *> mmu; 29711856Sbrandon.potter@amd.com Param<Addr> addr; 29811856Sbrandon.potter@amd.com Param<Addr> mask; 29911856Sbrandon.potter@amd.com 30011906SBrandon.Potter@amd.comEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 3018706Sandreas.hansson@arm.com 302360SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 30310931Sbrandon.potter@amd.com 304360SN/A INIT_PARAM(tsunami, "Tsunami"), 30510931Sbrandon.potter@amd.com INIT_PARAM(mmu, "Memory Controller"), 306360SN/A INIT_PARAM(addr, "Device Address"), 3071458SN/A INIT_PARAM(mask, "Address Mask") 308360SN/A 309360SN/AEND_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 310360SN/A 3111450SN/ACREATE_SIM_OBJECT(TsunamiCChip) 31211851Sbrandon.potter@amd.com{ 313360SN/A return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu); 3146701Sgblack@eecs.umich.edu} 31510931Sbrandon.potter@amd.com 3166701Sgblack@eecs.umich.eduREGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 3176701Sgblack@eecs.umich.edu