tsunami_cchip.cc revision 767
1/* $Id$ */ 2 3/* @file 4 * Tsunami CChip (processor, memory, or IO) 5 */ 6 7#include <deque> 8#include <string> 9#include <vector> 10 11#include "base/trace.hh" 12#include "cpu/exec_context.hh" 13#include "dev/console.hh" 14#include "dev/etherdev.hh" 15#include "dev/scsi_ctrl.hh" 16#include "dev/tlaser_clock.hh" 17#include "dev/tsunami_cchip.hh" 18#include "dev/tsunamireg.h" 19#include "dev/tsunami.hh" 20#include "mem/functional_mem/memory_control.hh" 21#include "sim/builder.hh" 22#include "sim/system.hh" 23 24using namespace std; 25 26TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, 27 Addr addr, Addr mask, MemoryController *mmu) 28 : MmapDevice(name, addr, mask, mmu), tsunami(t) 29{ 30 for(int i=0; i < Tsunami::Max_CPUs; i++) { 31 dim[i] = 0; 32 dir[i] = 0; 33 } 34 35 drir = 0; 36} 37 38Fault 39TsunamiCChip::read(MemReqPtr req, uint8_t *data) 40{ 41 DPRINTF(Tsunami, "cchip read va=%#x size=%d\n", 42 req->vaddr, req->size); 43 44 Addr daddr = (req->paddr & addr_mask) >> 6; 45// ExecContext *xc = req->xc; 46// int cpuid = xc->cpu_id; 47 48 switch (req->size) { 49 50 case sizeof(uint64_t): 51 switch(daddr) { 52 case TSDEV_CC_CSR: 53 *(uint64_t*)data = 0x0; 54 return No_Fault; 55 case TSDEV_CC_MTR: 56 panic("TSDEV_CC_MTR not implemeted\n"); 57 return No_Fault; 58 case TSDEV_CC_MISC: 59 panic("TSDEV_CC_MISC not implemented\n"); 60 return No_Fault; 61 case TSDEV_CC_AAR0: 62 case TSDEV_CC_AAR1: 63 case TSDEV_CC_AAR2: 64 case TSDEV_CC_AAR3: 65 panic("TSDEV_CC_AARx not implemeted\n"); 66 return No_Fault; 67 case TSDEV_CC_DIM0: 68 *(uint64_t*)data = dim[0]; 69 return No_Fault; 70 case TSDEV_CC_DIM1: 71 *(uint64_t*)data = dim[1]; 72 return No_Fault; 73 case TSDEV_CC_DIM2: 74 *(uint64_t*)data = dim[2]; 75 return No_Fault; 76 case TSDEV_CC_DIM3: 77 *(uint64_t*)data = dim[3]; 78 return No_Fault; 79 case TSDEV_CC_DIR0: 80 *(uint64_t*)data = dir[0]; 81 return No_Fault; 82 case TSDEV_CC_DIR1: 83 *(uint64_t*)data = dir[1]; 84 return No_Fault; 85 case TSDEV_CC_DIR2: 86 *(uint64_t*)data = dir[2]; 87 return No_Fault; 88 case TSDEV_CC_DIR3: 89 *(uint64_t*)data = dir[3]; 90 return No_Fault; 91 case TSDEV_CC_DRIR: 92 *(uint64_t*)data = drir; 93 return No_Fault; 94 case TSDEV_CC_PRBEN: 95 panic("TSDEV_CC_PRBEN not implemented\n"); 96 return No_Fault; 97 case TSDEV_CC_IIC0: 98 case TSDEV_CC_IIC1: 99 case TSDEV_CC_IIC2: 100 case TSDEV_CC_IIC3: 101 panic("TSDEV_CC_IICx not implemented\n"); 102 return No_Fault; 103 case TSDEV_CC_MPR0: 104 case TSDEV_CC_MPR1: 105 case TSDEV_CC_MPR2: 106 case TSDEV_CC_MPR3: 107 panic("TSDEV_CC_MPRx not implemented\n"); 108 return No_Fault; 109 } // uint64_t 110 111 break; 112 case sizeof(uint32_t): 113 case sizeof(uint16_t): 114 case sizeof(uint8_t): 115 default: 116 panic("invalid access size(?) for tsunami register!"); 117 } 118 DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 119 120 return No_Fault; 121} 122 123Fault 124TsunamiCChip::write(MemReqPtr req, const uint8_t *data) 125{ 126 DPRINTF(Tsunami, "Tsunami CChip write - va=%#x size=%d \n", 127 req->vaddr, req->size); 128 129 Addr daddr = (req->paddr & addr_mask) >> 6; 130 131 switch (req->size) { 132 133 case sizeof(uint64_t): 134 switch(daddr) { 135 case TSDEV_CC_CSR: 136 panic("TSDEV_CC_CSR write\n"); 137 return No_Fault; 138 case TSDEV_CC_MTR: 139 panic("TSDEV_CC_MTR write not implemented\n"); 140 return No_Fault; 141 case TSDEV_CC_MISC: 142 panic("TSDEV_CC_MISC write not implemented\n"); 143 return No_Fault; 144 case TSDEV_CC_AAR0: 145 case TSDEV_CC_AAR1: 146 case TSDEV_CC_AAR2: 147 case TSDEV_CC_AAR3: 148 panic("TSDEV_CC_AARx write not implemeted\n"); 149 return No_Fault; 150 case TSDEV_CC_DIM0: 151 dim[0] = *(uint64_t*)data; 152 return No_Fault; 153 case TSDEV_CC_DIM1: 154 dim[1] = *(uint64_t*)data; 155 return No_Fault; 156 case TSDEV_CC_DIM2: 157 dim[2] = *(uint64_t*)data; 158 return No_Fault; 159 case TSDEV_CC_DIM3: 160 dim[3] = *(uint64_t*)data; 161 return No_Fault; 162 case TSDEV_CC_DIR0: 163 case TSDEV_CC_DIR1: 164 case TSDEV_CC_DIR2: 165 case TSDEV_CC_DIR3: 166 panic("TSDEV_CC_DIR write not implemented\n"); 167 return No_Fault; 168 case TSDEV_CC_DRIR: 169 panic("TSDEV_CC_DRIR write not implemented\n"); 170 return No_Fault; 171 case TSDEV_CC_PRBEN: 172 panic("TSDEV_CC_PRBEN write not implemented\n"); 173 return No_Fault; 174 case TSDEV_CC_IIC0: 175 case TSDEV_CC_IIC1: 176 case TSDEV_CC_IIC2: 177 case TSDEV_CC_IIC3: 178 panic("TSDEV_CC_IICx write not implemented\n"); 179 return No_Fault; 180 case TSDEV_CC_MPR0: 181 case TSDEV_CC_MPR1: 182 case TSDEV_CC_MPR2: 183 case TSDEV_CC_MPR3: 184 panic("TSDEV_CC_MPRx write not implemented\n"); 185 return No_Fault; 186 } 187 188 break; 189 case sizeof(uint32_t): 190 case sizeof(uint16_t): 191 case sizeof(uint8_t): 192 default: 193 panic("invalid access size(?) for tsunami register!"); 194 } 195 196 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 197 198 return No_Fault; 199} 200 201void 202TsunamiCChip::serialize(std::ostream &os) 203{ 204 // code should be written 205} 206 207void 208TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 209{ 210 //code should be written 211} 212 213BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 214 215 SimObjectParam<Tsunami *> tsunami; 216 SimObjectParam<MemoryController *> mmu; 217 Param<Addr> addr; 218 Param<Addr> mask; 219 220END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 221 222BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 223 224 INIT_PARAM(tsunami, "Tsunami"), 225 INIT_PARAM(mmu, "Memory Controller"), 226 INIT_PARAM(addr, "Device Address"), 227 INIT_PARAM(mask, "Address Mask") 228 229END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 230 231CREATE_SIM_OBJECT(TsunamiCChip) 232{ 233 return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu); 234} 235 236REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 237