tsunami_cchip.cc revision 3540
1892SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3892SN/A * All rights reserved. 4892SN/A * 5892SN/A * Redistribution and use in source and binary forms, with or without 6892SN/A * modification, are permitted provided that the following conditions are 7892SN/A * met: redistributions of source code must retain the above copyright 8892SN/A * notice, this list of conditions and the following disclaimer; 9892SN/A * redistributions in binary form must reproduce the above copyright 10892SN/A * notice, this list of conditions and the following disclaimer in the 11892SN/A * documentation and/or other materials provided with the distribution; 12892SN/A * neither the name of the copyright holders nor the names of its 13892SN/A * contributors may be used to endorse or promote products derived from 14892SN/A * this software without specific prior written permission. 15892SN/A * 16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Ron Dreslinski 30892SN/A */ 31767SN/A 321730SN/A/** @file 33798SN/A * Emulation of the Tsunami CChip CSRs 34767SN/A */ 35767SN/A 36767SN/A#include <deque> 37767SN/A#include <string> 38767SN/A#include <vector> 39767SN/A 402432SN/A#include "arch/alpha/ev5.hh" 41767SN/A#include "base/trace.hh" 423348SN/A#include "cpu/intr_control.hh" 433348SN/A#include "cpu/thread_context.hh" 443540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 453540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 463540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 473348SN/A#include "mem/packet.hh" 483348SN/A#include "mem/packet_access.hh" 492523SN/A#include "mem/port.hh" 50767SN/A#include "sim/builder.hh" 51767SN/A#include "sim/system.hh" 52767SN/A 53767SN/Ausing namespace std; 542107SN/A//Should this be AlphaISA? 552107SN/Ausing namespace TheISA; 56767SN/A 572523SN/ATsunamiCChip::TsunamiCChip(Params *p) 582523SN/A : BasicPioDevice(p), tsunami(p->tsunami) 59767SN/A{ 602523SN/A pioSize = 0xfffffff; 61909SN/A 62767SN/A drir = 0; 631290SN/A ipint = 0; 641290SN/A itint = 0; 651290SN/A 661290SN/A for (int x = 0; x < Tsunami::Max_CPUs; x++) 671290SN/A { 681290SN/A dim[x] = 0; 691290SN/A dir[x] = 0; 701290SN/A } 71775SN/A 72775SN/A //Put back pointer in tsunami 73775SN/A tsunami->cchip = this; 74767SN/A} 75767SN/A 762523SN/ATick 773349SN/ATsunamiCChip::read(PacketPtr pkt) 78767SN/A{ 792641SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 80767SN/A 812641SN/A assert(pkt->result == Packet::Unknown); 822641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 831290SN/A 842641SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 852641SN/A Addr daddr = (pkt->getAddr() - pioAddr); 86767SN/A 872630SN/A pkt->allocate(); 882641SN/A switch (pkt->getSize()) { 89767SN/A 90767SN/A case sizeof(uint64_t): 911290SN/A if (daddr & TSDEV_CC_BDIMS) 921290SN/A { 932630SN/A pkt->set(dim[(daddr >> 4) & 0x3F]); 942523SN/A break; 951290SN/A } 961290SN/A 971290SN/A if (daddr & TSDEV_CC_BDIRS) 981290SN/A { 992630SN/A pkt->set(dir[(daddr >> 4) & 0x3F]); 1002523SN/A break; 1011290SN/A } 1021290SN/A 1031290SN/A switch(regnum) { 104767SN/A case TSDEV_CC_CSR: 1052630SN/A pkt->set(0x0); 1062523SN/A break; 107767SN/A case TSDEV_CC_MTR: 108767SN/A panic("TSDEV_CC_MTR not implemeted\n"); 1092523SN/A break; 110767SN/A case TSDEV_CC_MISC: 1112630SN/A pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF | 1122630SN/A (pkt->req->getCpuNum() & 0x3)); 1132523SN/A break; 114767SN/A case TSDEV_CC_AAR0: 115767SN/A case TSDEV_CC_AAR1: 116767SN/A case TSDEV_CC_AAR2: 117767SN/A case TSDEV_CC_AAR3: 1182630SN/A pkt->set(0); 1192523SN/A break; 120767SN/A case TSDEV_CC_DIM0: 1212630SN/A pkt->set(dim[0]); 1222523SN/A break; 123767SN/A case TSDEV_CC_DIM1: 1242630SN/A pkt->set(dim[1]); 1252523SN/A break; 126767SN/A case TSDEV_CC_DIM2: 1272630SN/A pkt->set(dim[2]); 1282523SN/A break; 129767SN/A case TSDEV_CC_DIM3: 1302630SN/A pkt->set(dim[3]); 1312523SN/A break; 132767SN/A case TSDEV_CC_DIR0: 1332630SN/A pkt->set(dir[0]); 1342523SN/A break; 135767SN/A case TSDEV_CC_DIR1: 1362630SN/A pkt->set(dir[1]); 1372523SN/A break; 138767SN/A case TSDEV_CC_DIR2: 1392630SN/A pkt->set(dir[2]); 1402523SN/A break; 141767SN/A case TSDEV_CC_DIR3: 1422630SN/A pkt->set(dir[3]); 1432523SN/A break; 144767SN/A case TSDEV_CC_DRIR: 1452630SN/A pkt->set(drir); 1462523SN/A break; 147767SN/A case TSDEV_CC_PRBEN: 148767SN/A panic("TSDEV_CC_PRBEN not implemented\n"); 1492523SN/A break; 150767SN/A case TSDEV_CC_IIC0: 151767SN/A case TSDEV_CC_IIC1: 152767SN/A case TSDEV_CC_IIC2: 153767SN/A case TSDEV_CC_IIC3: 154767SN/A panic("TSDEV_CC_IICx not implemented\n"); 1552523SN/A break; 156767SN/A case TSDEV_CC_MPR0: 157767SN/A case TSDEV_CC_MPR1: 158767SN/A case TSDEV_CC_MPR2: 159767SN/A case TSDEV_CC_MPR3: 160767SN/A panic("TSDEV_CC_MPRx not implemented\n"); 1612523SN/A break; 1621290SN/A case TSDEV_CC_IPIR: 1632630SN/A pkt->set(ipint); 1642523SN/A break; 1651290SN/A case TSDEV_CC_ITIR: 1662630SN/A pkt->set(itint); 1672523SN/A break; 168768SN/A default: 169768SN/A panic("default in cchip read reached, accessing 0x%x\n"); 170767SN/A } // uint64_t 171767SN/A 172767SN/A break; 173767SN/A case sizeof(uint32_t): 174767SN/A case sizeof(uint16_t): 175767SN/A case sizeof(uint8_t): 176767SN/A default: 177768SN/A panic("invalid access size(?) for tsunami register!\n"); 178767SN/A } 1792549SN/A DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", 1802641SN/A regnum, pkt->getSize(), pkt->get<uint64_t>()); 181767SN/A 1822641SN/A pkt->result = Packet::Success; 1832523SN/A return pioDelay; 184767SN/A} 185767SN/A 1862523SN/ATick 1873349SN/ATsunamiCChip::write(PacketPtr pkt) 188767SN/A{ 1892641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1902641SN/A Addr daddr = pkt->getAddr() - pioAddr; 1912641SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 1922539SN/A 1932523SN/A 1942641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 1952523SN/A 1962641SN/A DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 197767SN/A 198830SN/A bool supportedWrite = false; 199830SN/A 200767SN/A 2012539SN/A if (daddr & TSDEV_CC_BDIMS) 2022539SN/A { 2032539SN/A int number = (daddr >> 4) & 0x3F; 2041290SN/A 2052539SN/A uint64_t bitvector; 2062539SN/A uint64_t olddim; 2072539SN/A uint64_t olddir; 2081290SN/A 2092539SN/A olddim = dim[number]; 2102539SN/A olddir = dir[number]; 2112630SN/A dim[number] = pkt->get<uint64_t>(); 2122539SN/A dir[number] = dim[number] & drir; 2132539SN/A for(int x = 0; x < Tsunami::Max_CPUs; x++) 2142539SN/A { 2152539SN/A bitvector = ULL(1) << x; 2162539SN/A // Figure out which bits have changed 2172539SN/A if ((dim[number] & bitvector) != (olddim & bitvector)) 2182539SN/A { 2192539SN/A // The bit is now set and it wasn't before (set) 2202539SN/A if((dim[number] & bitvector) && (dir[number] & bitvector)) 2212539SN/A { 2222539SN/A tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 2232539SN/A DPRINTF(Tsunami, "dim write resulting in posting dir" 2242539SN/A " interrupt to cpu %d\n", number); 2252539SN/A } 2262539SN/A else if ((olddir & bitvector) && 2272539SN/A !(dir[number] & bitvector)) 2282539SN/A { 2292539SN/A // The bit was set and now its now clear and 2302539SN/A // we were interrupting on that bit before 2312539SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 2322539SN/A DPRINTF(Tsunami, "dim write resulting in clear" 2332539SN/A " dir interrupt to cpu %d\n", number); 2341290SN/A 2351074SN/A } 2361074SN/A 2372539SN/A 2382539SN/A } 2392539SN/A } 2402539SN/A } else { 2412539SN/A switch(regnum) { 2422539SN/A case TSDEV_CC_CSR: 2432539SN/A panic("TSDEV_CC_CSR write\n"); 2442539SN/A case TSDEV_CC_MTR: 2452539SN/A panic("TSDEV_CC_MTR write not implemented\n"); 2462539SN/A case TSDEV_CC_MISC: 2472539SN/A uint64_t ipreq; 2482630SN/A ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 2492539SN/A //If it is bit 12-15, this is an IPI post 2502539SN/A if (ipreq) { 2512539SN/A reqIPI(ipreq); 2522539SN/A supportedWrite = true; 2532539SN/A } 2542539SN/A 2552539SN/A //If it is bit 8-11, this is an IPI clear 2562539SN/A uint64_t ipintr; 2572630SN/A ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 2582539SN/A if (ipintr) { 2592539SN/A clearIPI(ipintr); 2602539SN/A supportedWrite = true; 2612539SN/A } 2622539SN/A 2632539SN/A //If it is the 4-7th bit, clear the RTC interrupt 2642539SN/A uint64_t itintr; 2652630SN/A itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 2662539SN/A if (itintr) { 2672539SN/A clearITI(itintr); 2682539SN/A supportedWrite = true; 2692539SN/A } 2702539SN/A 2712539SN/A // ignore NXMs 2722630SN/A if (pkt->get<uint64_t>() & 0x10000000) 2732539SN/A supportedWrite = true; 2742539SN/A 2752539SN/A if(!supportedWrite) 2762539SN/A panic("TSDEV_CC_MISC write not implemented\n"); 2772539SN/A 2782549SN/A break; 2792539SN/A case TSDEV_CC_AAR0: 2802539SN/A case TSDEV_CC_AAR1: 2812539SN/A case TSDEV_CC_AAR2: 2822539SN/A case TSDEV_CC_AAR3: 2832539SN/A panic("TSDEV_CC_AARx write not implemeted\n"); 2842539SN/A case TSDEV_CC_DIM0: 2852539SN/A case TSDEV_CC_DIM1: 2862539SN/A case TSDEV_CC_DIM2: 2872539SN/A case TSDEV_CC_DIM3: 2882539SN/A int number; 2892539SN/A if(regnum == TSDEV_CC_DIM0) 2902539SN/A number = 0; 2912539SN/A else if(regnum == TSDEV_CC_DIM1) 2922539SN/A number = 1; 2932539SN/A else if(regnum == TSDEV_CC_DIM2) 2942539SN/A number = 2; 2952539SN/A else 2962539SN/A number = 3; 2972539SN/A 2982539SN/A uint64_t bitvector; 2992539SN/A uint64_t olddim; 3002539SN/A uint64_t olddir; 3012539SN/A 3022539SN/A olddim = dim[number]; 3032539SN/A olddir = dir[number]; 3042630SN/A dim[number] = pkt->get<uint64_t>(); 3052539SN/A dir[number] = dim[number] & drir; 3062539SN/A for(int x = 0; x < 64; x++) 3072539SN/A { 3082539SN/A bitvector = ULL(1) << x; 3092539SN/A // Figure out which bits have changed 3102539SN/A if ((dim[number] & bitvector) != (olddim & bitvector)) 3112539SN/A { 3122539SN/A // The bit is now set and it wasn't before (set) 3132539SN/A if((dim[number] & bitvector) && (dir[number] & bitvector)) 3142539SN/A { 3152539SN/A tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 3162539SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 3172539SN/A } 3182539SN/A else if ((olddir & bitvector) && 3192539SN/A !(dir[number] & bitvector)) 3202539SN/A { 3212539SN/A // The bit was set and now its now clear and 3222539SN/A // we were interrupting on that bit before 3232539SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 3242539SN/A DPRINTF(Tsunami, "dim write resulting in clear" 3252539SN/A " dir interrupt to cpu %d\n", 3262539SN/A x); 3272539SN/A 3282539SN/A } 3292539SN/A 3302539SN/A 3312539SN/A } 3321074SN/A } 3332539SN/A break; 3342539SN/A case TSDEV_CC_DIR0: 3352539SN/A case TSDEV_CC_DIR1: 3362539SN/A case TSDEV_CC_DIR2: 3372539SN/A case TSDEV_CC_DIR3: 3382539SN/A panic("TSDEV_CC_DIR write not implemented\n"); 3392539SN/A case TSDEV_CC_DRIR: 3402539SN/A panic("TSDEV_CC_DRIR write not implemented\n"); 3412539SN/A case TSDEV_CC_PRBEN: 3422539SN/A panic("TSDEV_CC_PRBEN write not implemented\n"); 3432539SN/A case TSDEV_CC_IIC0: 3442539SN/A case TSDEV_CC_IIC1: 3452539SN/A case TSDEV_CC_IIC2: 3462539SN/A case TSDEV_CC_IIC3: 3472539SN/A panic("TSDEV_CC_IICx write not implemented\n"); 3482539SN/A case TSDEV_CC_MPR0: 3492539SN/A case TSDEV_CC_MPR1: 3502539SN/A case TSDEV_CC_MPR2: 3512539SN/A case TSDEV_CC_MPR3: 3522539SN/A panic("TSDEV_CC_MPRx write not implemented\n"); 3532539SN/A case TSDEV_CC_IPIR: 3542630SN/A clearIPI(pkt->get<uint64_t>()); 3552539SN/A break; 3562539SN/A case TSDEV_CC_ITIR: 3572630SN/A clearITI(pkt->get<uint64_t>()); 3582539SN/A break; 3592539SN/A case TSDEV_CC_IPIQ: 3602630SN/A reqIPI(pkt->get<uint64_t>()); 3612539SN/A break; 3622539SN/A default: 3632539SN/A panic("default in cchip read reached, accessing 0x%x\n"); 3642539SN/A } // swtich(regnum) 3652539SN/A } // not BIG_TSUNAMI write 3662641SN/A pkt->result = Packet::Success; 3672539SN/A return pioDelay; 368767SN/A} 369767SN/A 370767SN/Avoid 3711290SN/ATsunamiCChip::clearIPI(uint64_t ipintr) 3721290SN/A{ 3732680SN/A int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size(); 3741290SN/A assert(numcpus <= Tsunami::Max_CPUs); 3751290SN/A 3761290SN/A if (ipintr) { 3771290SN/A for (int cpunum=0; cpunum < numcpus; cpunum++) { 3781290SN/A // Check each cpu bit 3791290SN/A uint64_t cpumask = ULL(1) << cpunum; 3801290SN/A if (ipintr & cpumask) { 3811290SN/A // Check if there is a pending ipi 3821290SN/A if (ipint & cpumask) { 3831290SN/A ipint &= ~cpumask; 3841290SN/A tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 3851290SN/A DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 3861290SN/A } 3871290SN/A else 3881290SN/A warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 3891290SN/A } 3901290SN/A } 3911290SN/A } 3921290SN/A else 3931290SN/A panic("Big IPI Clear, but not processors indicated\n"); 3941290SN/A} 3951290SN/A 3961290SN/Avoid 3971290SN/ATsunamiCChip::clearITI(uint64_t itintr) 3981290SN/A{ 3992680SN/A int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size(); 4001290SN/A assert(numcpus <= Tsunami::Max_CPUs); 4011290SN/A 4021290SN/A if (itintr) { 4031290SN/A for (int i=0; i < numcpus; i++) { 4041290SN/A uint64_t cpumask = ULL(1) << i; 4051290SN/A if (itintr & cpumask & itint) { 4061290SN/A tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 4071290SN/A itint &= ~cpumask; 4081290SN/A DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 4091290SN/A } 4101290SN/A } 4111290SN/A } 4121290SN/A else 4131290SN/A panic("Big ITI Clear, but not processors indicated\n"); 4141290SN/A} 4151290SN/A 4161290SN/Avoid 4171290SN/ATsunamiCChip::reqIPI(uint64_t ipreq) 4181290SN/A{ 4192680SN/A int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size(); 4201290SN/A assert(numcpus <= Tsunami::Max_CPUs); 4211290SN/A 4221290SN/A if (ipreq) { 4231290SN/A for (int cpunum=0; cpunum < numcpus; cpunum++) { 4241290SN/A // Check each cpu bit 4251290SN/A uint64_t cpumask = ULL(1) << cpunum; 4261290SN/A if (ipreq & cpumask) { 4271290SN/A // Check if there is already an ipi (bits 8:11) 4281290SN/A if (!(ipint & cpumask)) { 4291290SN/A ipint |= cpumask; 4301290SN/A tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 4311290SN/A DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 4321290SN/A } 4331290SN/A else 4341290SN/A warn("post IPI for CPU=%d, but IPI already\n", cpunum); 4351290SN/A } 4361290SN/A } 4371290SN/A } 4381290SN/A else 4391290SN/A panic("Big IPI Request, but not processors indicated\n"); 4401290SN/A} 4411290SN/A 4421290SN/A 4431290SN/Avoid 444831SN/ATsunamiCChip::postRTC() 445831SN/A{ 4462680SN/A int size = tsunami->intrctrl->cpu->system->threadContexts.size(); 4471290SN/A assert(size <= Tsunami::Max_CPUs); 448831SN/A 449831SN/A for (int i = 0; i < size; i++) { 4501290SN/A uint64_t cpumask = ULL(1) << i; 4512539SN/A if (!(cpumask & itint)) { 4522539SN/A itint |= cpumask; 4532539SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 4542539SN/A DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); 4552539SN/A } 456831SN/A } 457831SN/A 458831SN/A} 459831SN/A 460831SN/Avoid 461817SN/ATsunamiCChip::postDRIR(uint32_t interrupt) 462777SN/A{ 4631290SN/A uint64_t bitvector = ULL(1) << interrupt; 4642680SN/A uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size(); 4651290SN/A assert(size <= Tsunami::Max_CPUs); 466777SN/A drir |= bitvector; 4671290SN/A 468831SN/A for(int i=0; i < size; i++) { 469817SN/A dir[i] = dim[i] & drir; 4702539SN/A if (dim[i] & bitvector) { 4712539SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 4722539SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 473817SN/A "interrupt %d\n",i, interrupt); 4742539SN/A } 475777SN/A } 476777SN/A} 477777SN/A 478777SN/Avoid 479817SN/ATsunamiCChip::clearDRIR(uint32_t interrupt) 480777SN/A{ 4811290SN/A uint64_t bitvector = ULL(1) << interrupt; 4822680SN/A uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size(); 4831290SN/A assert(size <= Tsunami::Max_CPUs); 4841290SN/A 485817SN/A if (drir & bitvector) 486817SN/A { 487817SN/A drir &= ~bitvector; 488831SN/A for(int i=0; i < size; i++) { 4892539SN/A if (dir[i] & bitvector) { 4902539SN/A tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 4912539SN/A DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 492817SN/A "interrupt %d\n",i, interrupt); 493777SN/A 4942539SN/A } 4952539SN/A dir[i] = dim[i] & drir; 496777SN/A } 497777SN/A } 498817SN/A else 499817SN/A DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 500777SN/A} 501777SN/A 502909SN/A 503777SN/Avoid 504767SN/ATsunamiCChip::serialize(std::ostream &os) 505767SN/A{ 506811SN/A SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 507811SN/A SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 5081290SN/A SERIALIZE_SCALAR(ipint); 5091290SN/A SERIALIZE_SCALAR(itint); 510811SN/A SERIALIZE_SCALAR(drir); 511767SN/A} 512767SN/A 513767SN/Avoid 514767SN/ATsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 515767SN/A{ 516811SN/A UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 517811SN/A UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 5181290SN/A UNSERIALIZE_SCALAR(ipint); 5191290SN/A UNSERIALIZE_SCALAR(itint); 520811SN/A UNSERIALIZE_SCALAR(drir); 521767SN/A} 522767SN/A 523767SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 524767SN/A 5252539SN/A Param<Addr> pio_addr; 5262539SN/A Param<Tick> pio_latency; 5272539SN/A SimObjectParam<Platform *> platform; 5282539SN/A SimObjectParam<System *> system; 529775SN/A SimObjectParam<Tsunami *> tsunami; 530767SN/A 531767SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 532767SN/A 533767SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 534767SN/A 5352539SN/A INIT_PARAM(pio_addr, "Device Address"), 5362539SN/A INIT_PARAM(pio_latency, "Programmed IO latency"), 5372539SN/A INIT_PARAM(platform, "platform"), 5382539SN/A INIT_PARAM(system, "system object"), 5392539SN/A INIT_PARAM(tsunami, "Tsunami") 540767SN/A 541767SN/AEND_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 542767SN/A 543767SN/ACREATE_SIM_OBJECT(TsunamiCChip) 544767SN/A{ 5452539SN/A TsunamiCChip::Params *p = new TsunamiCChip::Params; 5462539SN/A p->name = getInstanceName(); 5472539SN/A p->pio_addr = pio_addr; 5482539SN/A p->pio_delay = pio_latency; 5492539SN/A p->platform = platform; 5502539SN/A p->system = system; 5512539SN/A p->tsunami = tsunami; 5522539SN/A return new TsunamiCChip(p); 553767SN/A} 554767SN/A 555767SN/AREGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 556