tsunami_cchip.cc revision 2432
110859Sandreas.sandberg@arm.com/* 210859Sandreas.sandberg@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310859Sandreas.sandberg@arm.com * All rights reserved. 410859Sandreas.sandberg@arm.com * 510859Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 610859Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 710859Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 810859Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 910859Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1010859Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1110859Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1210859Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1310859Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1410859Sandreas.sandberg@arm.com * this software without specific prior written permission. 1510859Sandreas.sandberg@arm.com * 1610859Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710859Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810859Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910859Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010859Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110859Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210859Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310859Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410859Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510859Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610859Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710859Sandreas.sandberg@arm.com */ 2810859Sandreas.sandberg@arm.com 2910859Sandreas.sandberg@arm.com/** @file 3010859Sandreas.sandberg@arm.com * Emulation of the Tsunami CChip CSRs 3110859Sandreas.sandberg@arm.com */ 3210859Sandreas.sandberg@arm.com 3310859Sandreas.sandberg@arm.com#include <deque> 3410859Sandreas.sandberg@arm.com#include <string> 3510859Sandreas.sandberg@arm.com#include <vector> 3610859Sandreas.sandberg@arm.com 3710859Sandreas.sandberg@arm.com#include "arch/alpha/ev5.hh" 3810859Sandreas.sandberg@arm.com#include "base/trace.hh" 3910859Sandreas.sandberg@arm.com#include "dev/tsunami_cchip.hh" 4010859Sandreas.sandberg@arm.com#include "dev/tsunamireg.h" 4110859Sandreas.sandberg@arm.com#include "dev/tsunami.hh" 4210859Sandreas.sandberg@arm.com#include "mem/bus/bus.hh" 4310859Sandreas.sandberg@arm.com#include "mem/bus/pio_interface.hh" 4410859Sandreas.sandberg@arm.com#include "mem/bus/pio_interface_impl.hh" 4510859Sandreas.sandberg@arm.com#include "mem/functional/memory_control.hh" 4610859Sandreas.sandberg@arm.com#include "cpu/exec_context.hh" 4710859Sandreas.sandberg@arm.com#include "cpu/intr_control.hh" 4810859Sandreas.sandberg@arm.com#include "sim/builder.hh" 4910859Sandreas.sandberg@arm.com#include "sim/system.hh" 5010859Sandreas.sandberg@arm.com 5110859Sandreas.sandberg@arm.comusing namespace std; 5210859Sandreas.sandberg@arm.com//Should this be AlphaISA? 5310859Sandreas.sandberg@arm.comusing namespace TheISA; 5410859Sandreas.sandberg@arm.com 5510859Sandreas.sandberg@arm.comTsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, 5610859Sandreas.sandberg@arm.com MemoryController *mmu, HierParams *hier, 5710859Sandreas.sandberg@arm.com Bus* pio_bus, Tick pio_latency) 5810859Sandreas.sandberg@arm.com : PioDevice(name, t), addr(a), tsunami(t) 5910859Sandreas.sandberg@arm.com{ 6010859Sandreas.sandberg@arm.com mmu->add_child(this, RangeSize(addr, size)); 6110859Sandreas.sandberg@arm.com 6210859Sandreas.sandberg@arm.com if (pio_bus) { 6310859Sandreas.sandberg@arm.com pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, 6410859Sandreas.sandberg@arm.com &TsunamiCChip::cacheAccess); 6510859Sandreas.sandberg@arm.com pioInterface->addAddrRange(RangeSize(addr, size)); 6610859Sandreas.sandberg@arm.com pioLatency = pio_latency * pio_bus->clockRate; 6710859Sandreas.sandberg@arm.com } 6810859Sandreas.sandberg@arm.com 6910859Sandreas.sandberg@arm.com drir = 0; 7010859Sandreas.sandberg@arm.com ipint = 0; 7110859Sandreas.sandberg@arm.com itint = 0; 7210859Sandreas.sandberg@arm.com 7310859Sandreas.sandberg@arm.com for (int x = 0; x < Tsunami::Max_CPUs; x++) 7410859Sandreas.sandberg@arm.com { 7510859Sandreas.sandberg@arm.com dim[x] = 0; 7610859Sandreas.sandberg@arm.com dir[x] = 0; 7710859Sandreas.sandberg@arm.com } 7810859Sandreas.sandberg@arm.com 7910859Sandreas.sandberg@arm.com //Put back pointer in tsunami 8010859Sandreas.sandberg@arm.com tsunami->cchip = this; 8110859Sandreas.sandberg@arm.com} 8210859Sandreas.sandberg@arm.com 8310859Sandreas.sandberg@arm.comFault 8410859Sandreas.sandberg@arm.comTsunamiCChip::read(MemReqPtr &req, uint8_t *data) 8510859Sandreas.sandberg@arm.com{ 8610859Sandreas.sandberg@arm.com DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); 8710859Sandreas.sandberg@arm.com 8810859Sandreas.sandberg@arm.com Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; 8910859Sandreas.sandberg@arm.com Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); 9010859Sandreas.sandberg@arm.com 9110859Sandreas.sandberg@arm.com ExecContext *xc = req->xc; 9210859Sandreas.sandberg@arm.com 9310859Sandreas.sandberg@arm.com switch (req->size) { 9410859Sandreas.sandberg@arm.com 9510859Sandreas.sandberg@arm.com case sizeof(uint64_t): 9610859Sandreas.sandberg@arm.com if (daddr & TSDEV_CC_BDIMS) 9710859Sandreas.sandberg@arm.com { 9810859Sandreas.sandberg@arm.com *(uint64_t*)data = dim[(daddr >> 4) & 0x3F]; 9910859Sandreas.sandberg@arm.com return NoFault; 10010859Sandreas.sandberg@arm.com } 10110859Sandreas.sandberg@arm.com 10210859Sandreas.sandberg@arm.com if (daddr & TSDEV_CC_BDIRS) 10310859Sandreas.sandberg@arm.com { 10410859Sandreas.sandberg@arm.com *(uint64_t*)data = dir[(daddr >> 4) & 0x3F]; 10510859Sandreas.sandberg@arm.com return NoFault; 10610859Sandreas.sandberg@arm.com } 10710859Sandreas.sandberg@arm.com 10810859Sandreas.sandberg@arm.com switch(regnum) { 10910859Sandreas.sandberg@arm.com case TSDEV_CC_CSR: 11010859Sandreas.sandberg@arm.com *(uint64_t*)data = 0x0; 11110859Sandreas.sandberg@arm.com return NoFault; 11210859Sandreas.sandberg@arm.com case TSDEV_CC_MTR: 11310859Sandreas.sandberg@arm.com panic("TSDEV_CC_MTR not implemeted\n"); 11410859Sandreas.sandberg@arm.com return NoFault; 11510859Sandreas.sandberg@arm.com case TSDEV_CC_MISC: 11610859Sandreas.sandberg@arm.com *(uint64_t*)data = (ipint << 8) & 0xF | 11710859Sandreas.sandberg@arm.com (itint << 4) & 0xF | 11810859Sandreas.sandberg@arm.com (xc->readCpuId() & 0x3); 11910859Sandreas.sandberg@arm.com return NoFault; 12010859Sandreas.sandberg@arm.com case TSDEV_CC_AAR0: 12110859Sandreas.sandberg@arm.com case TSDEV_CC_AAR1: 12210859Sandreas.sandberg@arm.com case TSDEV_CC_AAR2: 12310859Sandreas.sandberg@arm.com case TSDEV_CC_AAR3: 12410859Sandreas.sandberg@arm.com *(uint64_t*)data = 0; 12510859Sandreas.sandberg@arm.com return NoFault; 12610859Sandreas.sandberg@arm.com case TSDEV_CC_DIM0: 127 *(uint64_t*)data = dim[0]; 128 return NoFault; 129 case TSDEV_CC_DIM1: 130 *(uint64_t*)data = dim[1]; 131 return NoFault; 132 case TSDEV_CC_DIM2: 133 *(uint64_t*)data = dim[2]; 134 return NoFault; 135 case TSDEV_CC_DIM3: 136 *(uint64_t*)data = dim[3]; 137 return NoFault; 138 case TSDEV_CC_DIR0: 139 *(uint64_t*)data = dir[0]; 140 return NoFault; 141 case TSDEV_CC_DIR1: 142 *(uint64_t*)data = dir[1]; 143 return NoFault; 144 case TSDEV_CC_DIR2: 145 *(uint64_t*)data = dir[2]; 146 return NoFault; 147 case TSDEV_CC_DIR3: 148 *(uint64_t*)data = dir[3]; 149 return NoFault; 150 case TSDEV_CC_DRIR: 151 *(uint64_t*)data = drir; 152 return NoFault; 153 case TSDEV_CC_PRBEN: 154 panic("TSDEV_CC_PRBEN not implemented\n"); 155 return NoFault; 156 case TSDEV_CC_IIC0: 157 case TSDEV_CC_IIC1: 158 case TSDEV_CC_IIC2: 159 case TSDEV_CC_IIC3: 160 panic("TSDEV_CC_IICx not implemented\n"); 161 return NoFault; 162 case TSDEV_CC_MPR0: 163 case TSDEV_CC_MPR1: 164 case TSDEV_CC_MPR2: 165 case TSDEV_CC_MPR3: 166 panic("TSDEV_CC_MPRx not implemented\n"); 167 return NoFault; 168 case TSDEV_CC_IPIR: 169 *(uint64_t*)data = ipint; 170 return NoFault; 171 case TSDEV_CC_ITIR: 172 *(uint64_t*)data = itint; 173 return NoFault; 174 default: 175 panic("default in cchip read reached, accessing 0x%x\n"); 176 } // uint64_t 177 178 break; 179 case sizeof(uint32_t): 180 if (regnum == TSDEV_CC_DRIR) { 181 warn("accessing DRIR with 32 bit read, " 182 "hopefully your just reading this for timing"); 183 *(uint32_t*)data = drir; 184 } else 185 panic("invalid access size(?) for tsunami register!\n"); 186 return NoFault; 187 case sizeof(uint16_t): 188 case sizeof(uint8_t): 189 default: 190 panic("invalid access size(?) for tsunami register!\n"); 191 } 192 DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size); 193 194 return NoFault; 195} 196 197Fault 198TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) 199{ 200 DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", 201 req->vaddr, *(uint64_t*)data, req->size); 202 203 Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); 204 Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; 205 206 bool supportedWrite = false; 207 208 switch (req->size) { 209 210 case sizeof(uint64_t): 211 if (daddr & TSDEV_CC_BDIMS) 212 { 213 int number = (daddr >> 4) & 0x3F; 214 215 uint64_t bitvector; 216 uint64_t olddim; 217 uint64_t olddir; 218 219 olddim = dim[number]; 220 olddir = dir[number]; 221 dim[number] = *(uint64_t*)data; 222 dir[number] = dim[number] & drir; 223 for(int x = 0; x < Tsunami::Max_CPUs; x++) 224 { 225 bitvector = ULL(1) << x; 226 // Figure out which bits have changed 227 if ((dim[number] & bitvector) != (olddim & bitvector)) 228 { 229 // The bit is now set and it wasn't before (set) 230 if((dim[number] & bitvector) && (dir[number] & bitvector)) 231 { 232 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 233 DPRINTF(Tsunami, "dim write resulting in posting dir" 234 " interrupt to cpu %d\n", number); 235 } 236 else if ((olddir & bitvector) && 237 !(dir[number] & bitvector)) 238 { 239 // The bit was set and now its now clear and 240 // we were interrupting on that bit before 241 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 242 DPRINTF(Tsunami, "dim write resulting in clear" 243 " dir interrupt to cpu %d\n", number); 244 245 } 246 247 248 } 249 } 250 return NoFault; 251 } 252 253 switch(regnum) { 254 case TSDEV_CC_CSR: 255 panic("TSDEV_CC_CSR write\n"); 256 return NoFault; 257 case TSDEV_CC_MTR: 258 panic("TSDEV_CC_MTR write not implemented\n"); 259 return NoFault; 260 case TSDEV_CC_MISC: 261 uint64_t ipreq; 262 ipreq = (*(uint64_t*)data >> 12) & 0xF; 263 //If it is bit 12-15, this is an IPI post 264 if (ipreq) { 265 reqIPI(ipreq); 266 supportedWrite = true; 267 } 268 269 //If it is bit 8-11, this is an IPI clear 270 uint64_t ipintr; 271 ipintr = (*(uint64_t*)data >> 8) & 0xF; 272 if (ipintr) { 273 clearIPI(ipintr); 274 supportedWrite = true; 275 } 276 277 //If it is the 4-7th bit, clear the RTC interrupt 278 uint64_t itintr; 279 itintr = (*(uint64_t*)data >> 4) & 0xF; 280 if (itintr) { 281 clearITI(itintr); 282 supportedWrite = true; 283 } 284 285 // ignore NXMs 286 if (*(uint64_t*)data & 0x10000000) 287 supportedWrite = true; 288 289 if(!supportedWrite) 290 panic("TSDEV_CC_MISC write not implemented\n"); 291 292 return NoFault; 293 case TSDEV_CC_AAR0: 294 case TSDEV_CC_AAR1: 295 case TSDEV_CC_AAR2: 296 case TSDEV_CC_AAR3: 297 panic("TSDEV_CC_AARx write not implemeted\n"); 298 return NoFault; 299 case TSDEV_CC_DIM0: 300 case TSDEV_CC_DIM1: 301 case TSDEV_CC_DIM2: 302 case TSDEV_CC_DIM3: 303 int number; 304 if(regnum == TSDEV_CC_DIM0) 305 number = 0; 306 else if(regnum == TSDEV_CC_DIM1) 307 number = 1; 308 else if(regnum == TSDEV_CC_DIM2) 309 number = 2; 310 else 311 number = 3; 312 313 uint64_t bitvector; 314 uint64_t olddim; 315 uint64_t olddir; 316 317 olddim = dim[number]; 318 olddir = dir[number]; 319 dim[number] = *(uint64_t*)data; 320 dir[number] = dim[number] & drir; 321 for(int x = 0; x < 64; x++) 322 { 323 bitvector = ULL(1) << x; 324 // Figure out which bits have changed 325 if ((dim[number] & bitvector) != (olddim & bitvector)) 326 { 327 // The bit is now set and it wasn't before (set) 328 if((dim[number] & bitvector) && (dir[number] & bitvector)) 329 { 330 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 331 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 332 } 333 else if ((olddir & bitvector) && 334 !(dir[number] & bitvector)) 335 { 336 // The bit was set and now its now clear and 337 // we were interrupting on that bit before 338 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 339 DPRINTF(Tsunami, "dim write resulting in clear" 340 " dir interrupt to cpu %d\n", 341 x); 342 343 } 344 345 346 } 347 } 348 return NoFault; 349 case TSDEV_CC_DIR0: 350 case TSDEV_CC_DIR1: 351 case TSDEV_CC_DIR2: 352 case TSDEV_CC_DIR3: 353 panic("TSDEV_CC_DIR write not implemented\n"); 354 case TSDEV_CC_DRIR: 355 panic("TSDEV_CC_DRIR write not implemented\n"); 356 case TSDEV_CC_PRBEN: 357 panic("TSDEV_CC_PRBEN write not implemented\n"); 358 case TSDEV_CC_IIC0: 359 case TSDEV_CC_IIC1: 360 case TSDEV_CC_IIC2: 361 case TSDEV_CC_IIC3: 362 panic("TSDEV_CC_IICx write not implemented\n"); 363 case TSDEV_CC_MPR0: 364 case TSDEV_CC_MPR1: 365 case TSDEV_CC_MPR2: 366 case TSDEV_CC_MPR3: 367 panic("TSDEV_CC_MPRx write not implemented\n"); 368 case TSDEV_CC_IPIR: 369 clearIPI(*(uint64_t*)data); 370 return NoFault; 371 case TSDEV_CC_ITIR: 372 clearITI(*(uint64_t*)data); 373 return NoFault; 374 case TSDEV_CC_IPIQ: 375 reqIPI(*(uint64_t*)data); 376 return NoFault; 377 default: 378 panic("default in cchip read reached, accessing 0x%x\n"); 379 } 380 381 break; 382 case sizeof(uint32_t): 383 case sizeof(uint16_t): 384 case sizeof(uint8_t): 385 default: 386 panic("invalid access size(?) for tsunami register!\n"); 387 } 388 389 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 390 391 return NoFault; 392} 393 394void 395TsunamiCChip::clearIPI(uint64_t ipintr) 396{ 397 int numcpus = tsunami->intrctrl->cpu->system->execContexts.size(); 398 assert(numcpus <= Tsunami::Max_CPUs); 399 400 if (ipintr) { 401 for (int cpunum=0; cpunum < numcpus; cpunum++) { 402 // Check each cpu bit 403 uint64_t cpumask = ULL(1) << cpunum; 404 if (ipintr & cpumask) { 405 // Check if there is a pending ipi 406 if (ipint & cpumask) { 407 ipint &= ~cpumask; 408 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 409 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 410 } 411 else 412 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 413 } 414 } 415 } 416 else 417 panic("Big IPI Clear, but not processors indicated\n"); 418} 419 420void 421TsunamiCChip::clearITI(uint64_t itintr) 422{ 423 int numcpus = tsunami->intrctrl->cpu->system->execContexts.size(); 424 assert(numcpus <= Tsunami::Max_CPUs); 425 426 if (itintr) { 427 for (int i=0; i < numcpus; i++) { 428 uint64_t cpumask = ULL(1) << i; 429 if (itintr & cpumask & itint) { 430 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 431 itint &= ~cpumask; 432 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 433 } 434 } 435 } 436 else 437 panic("Big ITI Clear, but not processors indicated\n"); 438} 439 440void 441TsunamiCChip::reqIPI(uint64_t ipreq) 442{ 443 int numcpus = tsunami->intrctrl->cpu->system->execContexts.size(); 444 assert(numcpus <= Tsunami::Max_CPUs); 445 446 if (ipreq) { 447 for (int cpunum=0; cpunum < numcpus; cpunum++) { 448 // Check each cpu bit 449 uint64_t cpumask = ULL(1) << cpunum; 450 if (ipreq & cpumask) { 451 // Check if there is already an ipi (bits 8:11) 452 if (!(ipint & cpumask)) { 453 ipint |= cpumask; 454 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 455 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 456 } 457 else 458 warn("post IPI for CPU=%d, but IPI already\n", cpunum); 459 } 460 } 461 } 462 else 463 panic("Big IPI Request, but not processors indicated\n"); 464} 465 466 467void 468TsunamiCChip::postRTC() 469{ 470 int size = tsunami->intrctrl->cpu->system->execContexts.size(); 471 assert(size <= Tsunami::Max_CPUs); 472 473 for (int i = 0; i < size; i++) { 474 uint64_t cpumask = ULL(1) << i; 475 if (!(cpumask & itint)) { 476 itint |= cpumask; 477 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 478 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); 479 } 480 } 481 482} 483 484void 485TsunamiCChip::postDRIR(uint32_t interrupt) 486{ 487 uint64_t bitvector = ULL(1) << interrupt; 488 uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 489 assert(size <= Tsunami::Max_CPUs); 490 drir |= bitvector; 491 492 for(int i=0; i < size; i++) { 493 dir[i] = dim[i] & drir; 494 if (dim[i] & bitvector) { 495 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 496 DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 497 "interrupt %d\n",i, interrupt); 498 } 499 } 500} 501 502void 503TsunamiCChip::clearDRIR(uint32_t interrupt) 504{ 505 uint64_t bitvector = ULL(1) << interrupt; 506 uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 507 assert(size <= Tsunami::Max_CPUs); 508 509 if (drir & bitvector) 510 { 511 drir &= ~bitvector; 512 for(int i=0; i < size; i++) { 513 if (dir[i] & bitvector) { 514 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 515 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 516 "interrupt %d\n",i, interrupt); 517 518 } 519 dir[i] = dim[i] & drir; 520 } 521 } 522 else 523 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 524} 525 526Tick 527TsunamiCChip::cacheAccess(MemReqPtr &req) 528{ 529 return curTick + pioLatency; 530} 531 532 533void 534TsunamiCChip::serialize(std::ostream &os) 535{ 536 SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 537 SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 538 SERIALIZE_SCALAR(ipint); 539 SERIALIZE_SCALAR(itint); 540 SERIALIZE_SCALAR(drir); 541} 542 543void 544TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 545{ 546 UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 547 UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 548 UNSERIALIZE_SCALAR(ipint); 549 UNSERIALIZE_SCALAR(itint); 550 UNSERIALIZE_SCALAR(drir); 551} 552 553BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 554 555 SimObjectParam<Tsunami *> tsunami; 556 SimObjectParam<MemoryController *> mmu; 557 Param<Addr> addr; 558 SimObjectParam<Bus*> pio_bus; 559 Param<Tick> pio_latency; 560 SimObjectParam<HierParams *> hier; 561 562END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 563 564BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 565 566 INIT_PARAM(tsunami, "Tsunami"), 567 INIT_PARAM(mmu, "Memory Controller"), 568 INIT_PARAM(addr, "Device Address"), 569 INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), 570 INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), 571 INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 572 573END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 574 575CREATE_SIM_OBJECT(TsunamiCChip) 576{ 577 return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, 578 pio_bus, pio_latency); 579} 580 581REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 582