tsunami_cchip.cc revision 10905
1892SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3892SN/A * All rights reserved. 4892SN/A * 5892SN/A * Redistribution and use in source and binary forms, with or without 6892SN/A * modification, are permitted provided that the following conditions are 7892SN/A * met: redistributions of source code must retain the above copyright 8892SN/A * notice, this list of conditions and the following disclaimer; 9892SN/A * redistributions in binary form must reproduce the above copyright 10892SN/A * notice, this list of conditions and the following disclaimer in the 11892SN/A * documentation and/or other materials provided with the distribution; 12892SN/A * neither the name of the copyright holders nor the names of its 13892SN/A * contributors may be used to endorse or promote products derived from 14892SN/A * this software without specific prior written permission. 15892SN/A * 16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Ron Dreslinski 30892SN/A */ 31767SN/A 321730SN/A/** @file 33798SN/A * Emulation of the Tsunami CChip CSRs 34767SN/A */ 35767SN/A 36767SN/A#include <deque> 37767SN/A#include <string> 38767SN/A#include <vector> 39767SN/A 402432SN/A#include "arch/alpha/ev5.hh" 41767SN/A#include "base/trace.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 433348SN/A#include "cpu/intr_control.hh" 443348SN/A#include "cpu/thread_context.hh" 458232Snate@binkert.org#include "debug/IPI.hh" 468232Snate@binkert.org#include "debug/Tsunami.hh" 473540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 493540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 503348SN/A#include "mem/packet.hh" 513348SN/A#include "mem/packet_access.hh" 522523SN/A#include "mem/port.hh" 534762Snate@binkert.org#include "params/TsunamiCChip.hh" 54767SN/A#include "sim/system.hh" 55767SN/A 562107SN/A//Should this be AlphaISA? 572107SN/Ausing namespace TheISA; 58767SN/A 594762Snate@binkert.orgTsunamiCChip::TsunamiCChip(const Params *p) 609808Sstever@gmail.com : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami) 61767SN/A{ 62767SN/A drir = 0; 631290SN/A ipint = 0; 641290SN/A itint = 0; 651290SN/A 661290SN/A for (int x = 0; x < Tsunami::Max_CPUs; x++) 671290SN/A { 681290SN/A dim[x] = 0; 691290SN/A dir[x] = 0; 701290SN/A } 71775SN/A 72775SN/A //Put back pointer in tsunami 73775SN/A tsunami->cchip = this; 74767SN/A} 75767SN/A 762523SN/ATick 773349SN/ATsunamiCChip::read(PacketPtr pkt) 78767SN/A{ 792641SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 80767SN/A 812641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 821290SN/A 832641SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 842641SN/A Addr daddr = (pkt->getAddr() - pioAddr); 85767SN/A 862641SN/A switch (pkt->getSize()) { 87767SN/A 88767SN/A case sizeof(uint64_t): 893875Sbinkertn@umich.edu pkt->set<uint64_t>(0); 903875Sbinkertn@umich.edu 911290SN/A if (daddr & TSDEV_CC_BDIMS) 921290SN/A { 932630SN/A pkt->set(dim[(daddr >> 4) & 0x3F]); 942523SN/A break; 951290SN/A } 961290SN/A 971290SN/A if (daddr & TSDEV_CC_BDIRS) 981290SN/A { 992630SN/A pkt->set(dir[(daddr >> 4) & 0x3F]); 1002523SN/A break; 1011290SN/A } 1021290SN/A 1031290SN/A switch(regnum) { 104767SN/A case TSDEV_CC_CSR: 1052630SN/A pkt->set(0x0); 1062523SN/A break; 107767SN/A case TSDEV_CC_MTR: 108767SN/A panic("TSDEV_CC_MTR not implemeted\n"); 1092523SN/A break; 110767SN/A case TSDEV_CC_MISC: 1115570Snate@binkert.org pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | 1125714Shsul@eecs.umich.edu (pkt->req->contextId() & 0x3)); 1135714Shsul@eecs.umich.edu // currently, FS cannot handle MT so contextId and 1145714Shsul@eecs.umich.edu // cpuId are effectively the same, don't know if it will 1155714Shsul@eecs.umich.edu // matter if FS becomes MT enabled. I suspect no because 1165714Shsul@eecs.umich.edu // we are currently able to boot up to 64 procs anyway 1175714Shsul@eecs.umich.edu // which would render the CPUID of this register useless 1185714Shsul@eecs.umich.edu // anyway 1192523SN/A break; 120767SN/A case TSDEV_CC_AAR0: 121767SN/A case TSDEV_CC_AAR1: 122767SN/A case TSDEV_CC_AAR2: 123767SN/A case TSDEV_CC_AAR3: 1242630SN/A pkt->set(0); 1252523SN/A break; 126767SN/A case TSDEV_CC_DIM0: 1272630SN/A pkt->set(dim[0]); 1282523SN/A break; 129767SN/A case TSDEV_CC_DIM1: 1302630SN/A pkt->set(dim[1]); 1312523SN/A break; 132767SN/A case TSDEV_CC_DIM2: 1332630SN/A pkt->set(dim[2]); 1342523SN/A break; 135767SN/A case TSDEV_CC_DIM3: 1362630SN/A pkt->set(dim[3]); 1372523SN/A break; 138767SN/A case TSDEV_CC_DIR0: 1392630SN/A pkt->set(dir[0]); 1402523SN/A break; 141767SN/A case TSDEV_CC_DIR1: 1422630SN/A pkt->set(dir[1]); 1432523SN/A break; 144767SN/A case TSDEV_CC_DIR2: 1452630SN/A pkt->set(dir[2]); 1462523SN/A break; 147767SN/A case TSDEV_CC_DIR3: 1482630SN/A pkt->set(dir[3]); 1492523SN/A break; 150767SN/A case TSDEV_CC_DRIR: 1512630SN/A pkt->set(drir); 1522523SN/A break; 153767SN/A case TSDEV_CC_PRBEN: 154767SN/A panic("TSDEV_CC_PRBEN not implemented\n"); 1552523SN/A break; 156767SN/A case TSDEV_CC_IIC0: 157767SN/A case TSDEV_CC_IIC1: 158767SN/A case TSDEV_CC_IIC2: 159767SN/A case TSDEV_CC_IIC3: 160767SN/A panic("TSDEV_CC_IICx not implemented\n"); 1612523SN/A break; 162767SN/A case TSDEV_CC_MPR0: 163767SN/A case TSDEV_CC_MPR1: 164767SN/A case TSDEV_CC_MPR2: 165767SN/A case TSDEV_CC_MPR3: 166767SN/A panic("TSDEV_CC_MPRx not implemented\n"); 1672523SN/A break; 1681290SN/A case TSDEV_CC_IPIR: 1692630SN/A pkt->set(ipint); 1702523SN/A break; 1711290SN/A case TSDEV_CC_ITIR: 1722630SN/A pkt->set(itint); 1732523SN/A break; 174768SN/A default: 175768SN/A panic("default in cchip read reached, accessing 0x%x\n"); 176767SN/A } // uint64_t 177767SN/A 178767SN/A break; 179767SN/A case sizeof(uint32_t): 180767SN/A case sizeof(uint16_t): 181767SN/A case sizeof(uint8_t): 182767SN/A default: 183768SN/A panic("invalid access size(?) for tsunami register!\n"); 184767SN/A } 1852549SN/A DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", 1862641SN/A regnum, pkt->getSize(), pkt->get<uint64_t>()); 187767SN/A 1884870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1892523SN/A return pioDelay; 190767SN/A} 191767SN/A 1922523SN/ATick 1933349SN/ATsunamiCChip::write(PacketPtr pkt) 194767SN/A{ 1952641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1962641SN/A Addr daddr = pkt->getAddr() - pioAddr; 1972641SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 1982539SN/A 1992523SN/A 2002641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 2012523SN/A 2022641SN/A DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 203767SN/A 204830SN/A bool supportedWrite = false; 205830SN/A 206767SN/A 2072539SN/A if (daddr & TSDEV_CC_BDIMS) 2082539SN/A { 2092539SN/A int number = (daddr >> 4) & 0x3F; 2101290SN/A 2112539SN/A uint64_t bitvector; 2122539SN/A uint64_t olddim; 2132539SN/A uint64_t olddir; 2141290SN/A 2152539SN/A olddim = dim[number]; 2162539SN/A olddir = dir[number]; 2172630SN/A dim[number] = pkt->get<uint64_t>(); 2182539SN/A dir[number] = dim[number] & drir; 2192539SN/A for(int x = 0; x < Tsunami::Max_CPUs; x++) 2202539SN/A { 2212539SN/A bitvector = ULL(1) << x; 2222539SN/A // Figure out which bits have changed 2232539SN/A if ((dim[number] & bitvector) != (olddim & bitvector)) 2242539SN/A { 2252539SN/A // The bit is now set and it wasn't before (set) 2262539SN/A if((dim[number] & bitvector) && (dir[number] & bitvector)) 2272539SN/A { 2282539SN/A tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 2292539SN/A DPRINTF(Tsunami, "dim write resulting in posting dir" 2302539SN/A " interrupt to cpu %d\n", number); 2312539SN/A } 2322539SN/A else if ((olddir & bitvector) && 2332539SN/A !(dir[number] & bitvector)) 2342539SN/A { 2352539SN/A // The bit was set and now its now clear and 2362539SN/A // we were interrupting on that bit before 2372539SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 2382539SN/A DPRINTF(Tsunami, "dim write resulting in clear" 2392539SN/A " dir interrupt to cpu %d\n", number); 2401290SN/A 2411074SN/A } 2421074SN/A 2432539SN/A 2442539SN/A } 2452539SN/A } 2462539SN/A } else { 2472539SN/A switch(regnum) { 2482539SN/A case TSDEV_CC_CSR: 2492539SN/A panic("TSDEV_CC_CSR write\n"); 2502539SN/A case TSDEV_CC_MTR: 2512539SN/A panic("TSDEV_CC_MTR write not implemented\n"); 2522539SN/A case TSDEV_CC_MISC: 2532539SN/A uint64_t ipreq; 2542630SN/A ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 2552539SN/A //If it is bit 12-15, this is an IPI post 2562539SN/A if (ipreq) { 2572539SN/A reqIPI(ipreq); 2582539SN/A supportedWrite = true; 2592539SN/A } 2602539SN/A 2612539SN/A //If it is bit 8-11, this is an IPI clear 2622539SN/A uint64_t ipintr; 2632630SN/A ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 2642539SN/A if (ipintr) { 2652539SN/A clearIPI(ipintr); 2662539SN/A supportedWrite = true; 2672539SN/A } 2682539SN/A 2692539SN/A //If it is the 4-7th bit, clear the RTC interrupt 2702539SN/A uint64_t itintr; 2712630SN/A itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 2722539SN/A if (itintr) { 2732539SN/A clearITI(itintr); 2742539SN/A supportedWrite = true; 2752539SN/A } 2762539SN/A 2772539SN/A // ignore NXMs 2782630SN/A if (pkt->get<uint64_t>() & 0x10000000) 2792539SN/A supportedWrite = true; 2802539SN/A 2812539SN/A if(!supportedWrite) 2822539SN/A panic("TSDEV_CC_MISC write not implemented\n"); 2832539SN/A 2842549SN/A break; 2852539SN/A case TSDEV_CC_AAR0: 2862539SN/A case TSDEV_CC_AAR1: 2872539SN/A case TSDEV_CC_AAR2: 2882539SN/A case TSDEV_CC_AAR3: 2892539SN/A panic("TSDEV_CC_AARx write not implemeted\n"); 2902539SN/A case TSDEV_CC_DIM0: 2912539SN/A case TSDEV_CC_DIM1: 2922539SN/A case TSDEV_CC_DIM2: 2932539SN/A case TSDEV_CC_DIM3: 2942539SN/A int number; 2952539SN/A if(regnum == TSDEV_CC_DIM0) 2962539SN/A number = 0; 2972539SN/A else if(regnum == TSDEV_CC_DIM1) 2982539SN/A number = 1; 2992539SN/A else if(regnum == TSDEV_CC_DIM2) 3002539SN/A number = 2; 3012539SN/A else 3022539SN/A number = 3; 3032539SN/A 3042539SN/A uint64_t bitvector; 3052539SN/A uint64_t olddim; 3062539SN/A uint64_t olddir; 3072539SN/A 3082539SN/A olddim = dim[number]; 3092539SN/A olddir = dir[number]; 3102630SN/A dim[number] = pkt->get<uint64_t>(); 3112539SN/A dir[number] = dim[number] & drir; 3122539SN/A for(int x = 0; x < 64; x++) 3132539SN/A { 3142539SN/A bitvector = ULL(1) << x; 3152539SN/A // Figure out which bits have changed 3162539SN/A if ((dim[number] & bitvector) != (olddim & bitvector)) 3172539SN/A { 3182539SN/A // The bit is now set and it wasn't before (set) 3192539SN/A if((dim[number] & bitvector) && (dir[number] & bitvector)) 3202539SN/A { 3212539SN/A tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 3222539SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 3232539SN/A } 3242539SN/A else if ((olddir & bitvector) && 3252539SN/A !(dir[number] & bitvector)) 3262539SN/A { 3272539SN/A // The bit was set and now its now clear and 3282539SN/A // we were interrupting on that bit before 3292539SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 3302539SN/A DPRINTF(Tsunami, "dim write resulting in clear" 3312539SN/A " dir interrupt to cpu %d\n", 3322539SN/A x); 3332539SN/A 3342539SN/A } 3352539SN/A 3362539SN/A 3372539SN/A } 3381074SN/A } 3392539SN/A break; 3402539SN/A case TSDEV_CC_DIR0: 3412539SN/A case TSDEV_CC_DIR1: 3422539SN/A case TSDEV_CC_DIR2: 3432539SN/A case TSDEV_CC_DIR3: 3442539SN/A panic("TSDEV_CC_DIR write not implemented\n"); 3452539SN/A case TSDEV_CC_DRIR: 3462539SN/A panic("TSDEV_CC_DRIR write not implemented\n"); 3472539SN/A case TSDEV_CC_PRBEN: 3482539SN/A panic("TSDEV_CC_PRBEN write not implemented\n"); 3492539SN/A case TSDEV_CC_IIC0: 3502539SN/A case TSDEV_CC_IIC1: 3512539SN/A case TSDEV_CC_IIC2: 3522539SN/A case TSDEV_CC_IIC3: 3532539SN/A panic("TSDEV_CC_IICx write not implemented\n"); 3542539SN/A case TSDEV_CC_MPR0: 3552539SN/A case TSDEV_CC_MPR1: 3562539SN/A case TSDEV_CC_MPR2: 3572539SN/A case TSDEV_CC_MPR3: 3582539SN/A panic("TSDEV_CC_MPRx write not implemented\n"); 3592539SN/A case TSDEV_CC_IPIR: 3602630SN/A clearIPI(pkt->get<uint64_t>()); 3612539SN/A break; 3622539SN/A case TSDEV_CC_ITIR: 3632630SN/A clearITI(pkt->get<uint64_t>()); 3642539SN/A break; 3652539SN/A case TSDEV_CC_IPIQ: 3662630SN/A reqIPI(pkt->get<uint64_t>()); 3672539SN/A break; 3682539SN/A default: 3692539SN/A panic("default in cchip read reached, accessing 0x%x\n"); 3702539SN/A } // swtich(regnum) 3712539SN/A } // not BIG_TSUNAMI write 3724870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 3732539SN/A return pioDelay; 374767SN/A} 375767SN/A 376767SN/Avoid 3771290SN/ATsunamiCChip::clearIPI(uint64_t ipintr) 3781290SN/A{ 3794103Ssaidi@eecs.umich.edu int numcpus = sys->threadContexts.size(); 3801290SN/A assert(numcpus <= Tsunami::Max_CPUs); 3811290SN/A 3821290SN/A if (ipintr) { 3831290SN/A for (int cpunum=0; cpunum < numcpus; cpunum++) { 3841290SN/A // Check each cpu bit 3851290SN/A uint64_t cpumask = ULL(1) << cpunum; 3861290SN/A if (ipintr & cpumask) { 3871290SN/A // Check if there is a pending ipi 3881290SN/A if (ipint & cpumask) { 3891290SN/A ipint &= ~cpumask; 3901290SN/A tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 3911290SN/A DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 3921290SN/A } 3931290SN/A else 3941290SN/A warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 3951290SN/A } 3961290SN/A } 3971290SN/A } 3981290SN/A else 3991290SN/A panic("Big IPI Clear, but not processors indicated\n"); 4001290SN/A} 4011290SN/A 4021290SN/Avoid 4031290SN/ATsunamiCChip::clearITI(uint64_t itintr) 4041290SN/A{ 4054103Ssaidi@eecs.umich.edu int numcpus = sys->threadContexts.size(); 4061290SN/A assert(numcpus <= Tsunami::Max_CPUs); 4071290SN/A 4081290SN/A if (itintr) { 4091290SN/A for (int i=0; i < numcpus; i++) { 4101290SN/A uint64_t cpumask = ULL(1) << i; 4111290SN/A if (itintr & cpumask & itint) { 4121290SN/A tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 4131290SN/A itint &= ~cpumask; 4141290SN/A DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 4151290SN/A } 4161290SN/A } 4171290SN/A } 4181290SN/A else 4191290SN/A panic("Big ITI Clear, but not processors indicated\n"); 4201290SN/A} 4211290SN/A 4221290SN/Avoid 4231290SN/ATsunamiCChip::reqIPI(uint64_t ipreq) 4241290SN/A{ 4254103Ssaidi@eecs.umich.edu int numcpus = sys->threadContexts.size(); 4261290SN/A assert(numcpus <= Tsunami::Max_CPUs); 4271290SN/A 4281290SN/A if (ipreq) { 4291290SN/A for (int cpunum=0; cpunum < numcpus; cpunum++) { 4301290SN/A // Check each cpu bit 4311290SN/A uint64_t cpumask = ULL(1) << cpunum; 4321290SN/A if (ipreq & cpumask) { 4331290SN/A // Check if there is already an ipi (bits 8:11) 4341290SN/A if (!(ipint & cpumask)) { 4351290SN/A ipint |= cpumask; 4361290SN/A tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 4371290SN/A DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 4381290SN/A } 4391290SN/A else 4401290SN/A warn("post IPI for CPU=%d, but IPI already\n", cpunum); 4411290SN/A } 4421290SN/A } 4431290SN/A } 4441290SN/A else 4451290SN/A panic("Big IPI Request, but not processors indicated\n"); 4461290SN/A} 4471290SN/A 4481290SN/A 4491290SN/Avoid 450831SN/ATsunamiCChip::postRTC() 451831SN/A{ 4524103Ssaidi@eecs.umich.edu int size = sys->threadContexts.size(); 4531290SN/A assert(size <= Tsunami::Max_CPUs); 454831SN/A 455831SN/A for (int i = 0; i < size; i++) { 4561290SN/A uint64_t cpumask = ULL(1) << i; 4572539SN/A if (!(cpumask & itint)) { 4582539SN/A itint |= cpumask; 4592539SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 4604739Sstever@eecs.umich.edu DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i); 4612539SN/A } 462831SN/A } 463831SN/A 464831SN/A} 465831SN/A 466831SN/Avoid 467817SN/ATsunamiCChip::postDRIR(uint32_t interrupt) 468777SN/A{ 4691290SN/A uint64_t bitvector = ULL(1) << interrupt; 4704103Ssaidi@eecs.umich.edu uint64_t size = sys->threadContexts.size(); 4711290SN/A assert(size <= Tsunami::Max_CPUs); 472777SN/A drir |= bitvector; 4731290SN/A 474831SN/A for(int i=0; i < size; i++) { 475817SN/A dir[i] = dim[i] & drir; 4762539SN/A if (dim[i] & bitvector) { 4772539SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 4782539SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 479817SN/A "interrupt %d\n",i, interrupt); 4802539SN/A } 481777SN/A } 482777SN/A} 483777SN/A 484777SN/Avoid 485817SN/ATsunamiCChip::clearDRIR(uint32_t interrupt) 486777SN/A{ 4871290SN/A uint64_t bitvector = ULL(1) << interrupt; 4884103Ssaidi@eecs.umich.edu uint64_t size = sys->threadContexts.size(); 4891290SN/A assert(size <= Tsunami::Max_CPUs); 4901290SN/A 491817SN/A if (drir & bitvector) 492817SN/A { 493817SN/A drir &= ~bitvector; 494831SN/A for(int i=0; i < size; i++) { 4952539SN/A if (dir[i] & bitvector) { 4962539SN/A tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 4972539SN/A DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 498817SN/A "interrupt %d\n",i, interrupt); 499777SN/A 5002539SN/A } 5012539SN/A dir[i] = dim[i] & drir; 502777SN/A } 503777SN/A } 504817SN/A else 505817SN/A DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 506777SN/A} 507777SN/A 508909SN/A 509777SN/Avoid 51010905Sandreas.sandberg@arm.comTsunamiCChip::serialize(CheckpointOut &cp) const 511767SN/A{ 512811SN/A SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 513811SN/A SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 5141290SN/A SERIALIZE_SCALAR(ipint); 5151290SN/A SERIALIZE_SCALAR(itint); 516811SN/A SERIALIZE_SCALAR(drir); 517767SN/A} 518767SN/A 519767SN/Avoid 52010905Sandreas.sandberg@arm.comTsunamiCChip::unserialize(CheckpointIn &cp) 521767SN/A{ 522811SN/A UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 523811SN/A UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 5241290SN/A UNSERIALIZE_SCALAR(ipint); 5251290SN/A UNSERIALIZE_SCALAR(itint); 526811SN/A UNSERIALIZE_SCALAR(drir); 527767SN/A} 528767SN/A 5294762Snate@binkert.orgTsunamiCChip * 5304762Snate@binkert.orgTsunamiCChipParams::create() 531767SN/A{ 5324762Snate@binkert.org return new TsunamiCChip(this); 533767SN/A} 534