tsunami.cc revision 8741
1767SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3767SN/A * All rights reserved.
4767SN/A *
5767SN/A * Redistribution and use in source and binary forms, with or without
6767SN/A * modification, are permitted provided that the following conditions are
7767SN/A * met: redistributions of source code must retain the above copyright
8767SN/A * notice, this list of conditions and the following disclaimer;
9767SN/A * redistributions in binary form must reproduce the above copyright
10767SN/A * notice, this list of conditions and the following disclaimer in the
11767SN/A * documentation and/or other materials provided with the distribution;
12767SN/A * neither the name of the copyright holders nor the names of its
13767SN/A * contributors may be used to endorse or promote products derived from
14767SN/A * this software without specific prior written permission.
15767SN/A *
16767SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17767SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18767SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19767SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20767SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21767SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22767SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23767SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24767SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25767SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26767SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
29767SN/A */
30767SN/A
311763SN/A/** @file
321763SN/A * Implementation of Tsunami platform.
331730SN/A */
341730SN/A
35767SN/A#include <deque>
36767SN/A#include <string>
37767SN/A#include <vector>
38767SN/A
398741Sgblack@eecs.umich.edu#include "config/full_system.hh"
408741Sgblack@eecs.umich.edu
418741Sgblack@eecs.umich.edu#if FULL_SYSTEM //XXX AlphaSystem doesn't build in SE mode yet.
428741Sgblack@eecs.umich.edu#include "arch/alpha/system.hh"
438741Sgblack@eecs.umich.edu#endif
448741Sgblack@eecs.umich.edu
456658Snate@binkert.org#include "config/the_isa.hh"
46767SN/A#include "cpu/intr_control.hh"
478229Snate@binkert.org#include "dev/alpha/tsunami.hh"
483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh"
498229Snate@binkert.org#include "dev/alpha/tsunami_io.hh"
503540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_pchip.hh"
515478Snate@binkert.org#include "dev/terminal.hh"
52767SN/A
53767SN/Ausing namespace std;
542107SN/A//Should this be AlphaISA?
552107SN/Ausing namespace TheISA;
56767SN/A
575034Smilesck@eecs.umich.eduTsunami::Tsunami(const Params *p)
585034Smilesck@eecs.umich.edu    : Platform(p), system(p->system)
59767SN/A{
60767SN/A    for (int i = 0; i < Tsunami::Max_CPUs; i++)
61767SN/A        intr_sum_type[i] = 0;
62767SN/A}
63767SN/A
648741Sgblack@eecs.umich.eduvoid
658741Sgblack@eecs.umich.eduTsunami::init()
66891SN/A{
678741Sgblack@eecs.umich.edu#if FULL_SYSTEM //XXX AlphaSystem doesn't build in SE mode yet.
688741Sgblack@eecs.umich.edu    AlphaSystem *alphaSystem = dynamic_cast<AlphaSystem *>(system);
698741Sgblack@eecs.umich.edu    assert(alphaSystem);
708741Sgblack@eecs.umich.edu    alphaSystem->setIntrFreq(io->frequency());
718741Sgblack@eecs.umich.edu#endif
72891SN/A}
73891SN/A
74767SN/Avoid
75865SN/ATsunami::postConsoleInt()
76865SN/A{
77865SN/A    io->postPIC(0x10);
78865SN/A}
79865SN/A
80865SN/Avoid
81865SN/ATsunami::clearConsoleInt()
82865SN/A{
83865SN/A    io->clearPIC(0x10);
84865SN/A}
85865SN/A
86865SN/Avoid
871095SN/ATsunami::postPciInt(int line)
881095SN/A{
891599SN/A    cchip->postDRIR(line);
901095SN/A}
911095SN/A
921095SN/Avoid
931095SN/ATsunami::clearPciInt(int line)
941095SN/A{
951599SN/A    cchip->clearDRIR(line);
961149SN/A}
971149SN/A
981149SN/AAddr
991149SN/ATsunami::pciToDma(Addr pciAddr) const
1001149SN/A{
1011149SN/A    return pchip->translatePciToDma(pciAddr);
1021095SN/A}
1031095SN/A
1042846SN/A
1052846SN/AAddr
1065834Sgblack@eecs.umich.eduTsunami::calcPciConfigAddr(int bus, int dev, int func)
1072846SN/A{
1082846SN/A   return pchip->calcConfigAddr(bus, dev, func);
1092846SN/A}
1102846SN/A
1115834Sgblack@eecs.umich.eduAddr
1125834Sgblack@eecs.umich.eduTsunami::calcPciIOAddr(Addr addr)
1135834Sgblack@eecs.umich.edu{
1145834Sgblack@eecs.umich.edu   return pchip->calcIOAddr(addr);
1155834Sgblack@eecs.umich.edu}
1165834Sgblack@eecs.umich.edu
1175834Sgblack@eecs.umich.eduAddr
1185834Sgblack@eecs.umich.eduTsunami::calcPciMemAddr(Addr addr)
1195834Sgblack@eecs.umich.edu{
1205834Sgblack@eecs.umich.edu   return pchip->calcMemAddr(addr);
1215834Sgblack@eecs.umich.edu}
1225834Sgblack@eecs.umich.edu
1231095SN/Avoid
124767SN/ATsunami::serialize(std::ostream &os)
125767SN/A{
126767SN/A    SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
127767SN/A}
128767SN/A
129767SN/Avoid
130767SN/ATsunami::unserialize(Checkpoint *cp, const std::string &section)
131767SN/A{
132767SN/A    UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
133767SN/A}
134767SN/A
1354762Snate@binkert.orgTsunami *
1364762Snate@binkert.orgTsunamiParams::create()
137767SN/A{
1385034Smilesck@eecs.umich.edu    return new Tsunami(this);
139767SN/A}
140