tsunami.cc revision 3540
1767SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3767SN/A * All rights reserved. 4767SN/A * 5767SN/A * Redistribution and use in source and binary forms, with or without 6767SN/A * modification, are permitted provided that the following conditions are 7767SN/A * met: redistributions of source code must retain the above copyright 8767SN/A * notice, this list of conditions and the following disclaimer; 9767SN/A * redistributions in binary form must reproduce the above copyright 10767SN/A * notice, this list of conditions and the following disclaimer in the 11767SN/A * documentation and/or other materials provided with the distribution; 12767SN/A * neither the name of the copyright holders nor the names of its 13767SN/A * contributors may be used to endorse or promote products derived from 14767SN/A * this software without specific prior written permission. 15767SN/A * 16767SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17767SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18767SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19767SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20767SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21767SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22767SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23767SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24767SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25767SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26767SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 29767SN/A */ 30767SN/A 311763SN/A/** @file 321763SN/A * Implementation of Tsunami platform. 331730SN/A */ 341730SN/A 35767SN/A#include <deque> 36767SN/A#include <string> 37767SN/A#include <vector> 38767SN/A 39767SN/A#include "cpu/intr_control.hh" 40932SN/A#include "dev/simconsole.hh" 413540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 423540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_pchip.hh" 433540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh" 443540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 45767SN/A#include "sim/builder.hh" 46767SN/A#include "sim/system.hh" 47767SN/A 48767SN/Ausing namespace std; 492107SN/A//Should this be AlphaISA? 502107SN/Ausing namespace TheISA; 51767SN/A 522542SN/ATsunami::Tsunami(const string &name, System *s, IntrControl *ic) 532542SN/A : Platform(name, ic), system(s) 54767SN/A{ 55803SN/A // set the back pointer from the system to myself 56803SN/A system->platform = this; 57803SN/A 58767SN/A for (int i = 0; i < Tsunami::Max_CPUs; i++) 59767SN/A intr_sum_type[i] = 0; 60767SN/A} 61767SN/A 62891SN/ATick 63891SN/ATsunami::intrFrequency() 64891SN/A{ 65891SN/A return io->frequency(); 66891SN/A} 67891SN/A 68767SN/Avoid 69865SN/ATsunami::postConsoleInt() 70865SN/A{ 71865SN/A io->postPIC(0x10); 72865SN/A} 73865SN/A 74865SN/Avoid 75865SN/ATsunami::clearConsoleInt() 76865SN/A{ 77865SN/A io->clearPIC(0x10); 78865SN/A} 79865SN/A 80865SN/Avoid 811095SN/ATsunami::postPciInt(int line) 821095SN/A{ 831599SN/A cchip->postDRIR(line); 841095SN/A} 851095SN/A 861095SN/Avoid 871095SN/ATsunami::clearPciInt(int line) 881095SN/A{ 891599SN/A cchip->clearDRIR(line); 901149SN/A} 911149SN/A 921149SN/AAddr 931149SN/ATsunami::pciToDma(Addr pciAddr) const 941149SN/A{ 951149SN/A return pchip->translatePciToDma(pciAddr); 961095SN/A} 971095SN/A 982846SN/A 992846SN/AAddr 1002846SN/ATsunami::calcConfigAddr(int bus, int dev, int func) 1012846SN/A{ 1022846SN/A return pchip->calcConfigAddr(bus, dev, func); 1032846SN/A} 1042846SN/A 1051095SN/Avoid 106767SN/ATsunami::serialize(std::ostream &os) 107767SN/A{ 108767SN/A SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); 109767SN/A} 110767SN/A 111767SN/Avoid 112767SN/ATsunami::unserialize(Checkpoint *cp, const std::string §ion) 113767SN/A{ 114767SN/A UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); 115767SN/A} 116767SN/A 117767SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami) 118767SN/A 119803SN/A SimObjectParam<System *> system; 120767SN/A SimObjectParam<IntrControl *> intrctrl; 121767SN/A 122767SN/AEND_DECLARE_SIM_OBJECT_PARAMS(Tsunami) 123767SN/A 124767SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami) 125767SN/A 126803SN/A INIT_PARAM(system, "system"), 1272542SN/A INIT_PARAM(intrctrl, "interrupt controller") 128767SN/A 129767SN/AEND_INIT_SIM_OBJECT_PARAMS(Tsunami) 130767SN/A 131767SN/ACREATE_SIM_OBJECT(Tsunami) 132767SN/A{ 1332542SN/A return new Tsunami(getInstanceName(), system, intrctrl); 134767SN/A} 135767SN/A 136767SN/AREGISTER_SIM_OBJECT("Tsunami", Tsunami) 137