backdoor.hh revision 2512
11689SN/A/*
21689SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
39915Ssteve.reinhardt@amd.com * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
271689SN/A */
282665Ssaidi@eecs.umich.edu
292665Ssaidi@eecs.umich.edu/** @file
302665Ssaidi@eecs.umich.edu * System Console Interface
311689SN/A */
321689SN/A
332292SN/A#ifndef __ALPHA_CONSOLE_HH__
342292SN/A#define __ALPHA_CONSOLE_HH__
351060SN/A
366658Snate@binkert.org#include "base/range.hh"
376658Snate@binkert.org#include "dev/alpha_access.h"
382165SN/A#include "dev/io_device.hh"
398793Sgblack@eecs.umich.edu#include "sim/host.hh"
402669Sktlim@umich.edu#include "sim/sim_object.hh"
411681SN/A
426658Snate@binkert.orgclass BaseCPU;
431717SN/Aclass SimConsole;
448232Snate@binkert.orgclass AlphaSystem;
451060SN/Aclass SimpleDisk;
469919Ssteve.reinhardt@amd.comclass MemoryController;
479919Ssteve.reinhardt@amd.com
482292SN/A/**
492292SN/A * Memory mapped interface to the system console. This device
502292SN/A * represents a shared data region between the OS Kernel and the
511060SN/A * System Console.
521060SN/A *
539915Ssteve.reinhardt@amd.com * The system console is a small standalone program that is initially
549915Ssteve.reinhardt@amd.com * run when the system boots.  It contains the necessary code to
552107SN/A * access the boot disk, to read/write from the console, and to pass
562107SN/A * boot parameters to the kernel.
572669Sktlim@umich.edu *
582159SN/A * This version of the system console is very different from the one
592669Sktlim@umich.edu * that would be found in a real system.  Many of the functions use
602669Sktlim@umich.edu * some sort of backdoor to get their job done.  For example, reading
612669Sktlim@umich.edu * from the boot device on a real system would require a minimal
622669Sktlim@umich.edu * device driver to access the disk controller, but since we have a
631060SN/A * simulator here, we are able to bypass the disk controller and
649915Ssteve.reinhardt@amd.com * access the disk image directly.  There are also some things like
659919Ssteve.reinhardt@amd.com * reading the kernel off the disk image into memory that are normally
661060SN/A * taken care of by the console that are now taken care of by the
679915Ssteve.reinhardt@amd.com * simulator.
689919Ssteve.reinhardt@amd.com *
699915Ssteve.reinhardt@amd.com * These shortcuts are acceptable since the system console is
709915Ssteve.reinhardt@amd.com * primarily used doing boot before the kernel has loaded its device
719915Ssteve.reinhardt@amd.com * drivers.
729915Ssteve.reinhardt@amd.com */
739915Ssteve.reinhardt@amd.comclass AlphaConsole : public BasePioDevice
749915Ssteve.reinhardt@amd.com{
759915Ssteve.reinhardt@amd.com  protected:
769915Ssteve.reinhardt@amd.com    struct Access : public AlphaAccess
779919Ssteve.reinhardt@amd.com    {
789919Ssteve.reinhardt@amd.com        void serialize(std::ostream &os);
799919Ssteve.reinhardt@amd.com        void unserialize(Checkpoint *cp, const std::string &section);
809919Ssteve.reinhardt@amd.com    };
819919Ssteve.reinhardt@amd.com
829919Ssteve.reinhardt@amd.com    union {
839915Ssteve.reinhardt@amd.com        Access *alphaAccess;
849915Ssteve.reinhardt@amd.com        uint8_t *consoleData;
859915Ssteve.reinhardt@amd.com    };
869915Ssteve.reinhardt@amd.com
879915Ssteve.reinhardt@amd.com    /** the disk must be accessed from the console */
889915Ssteve.reinhardt@amd.com    SimpleDisk *disk;
891060SN/A
902292SN/A    /** the system console (the terminal) is accessable from the console */
912292SN/A    SimConsole *console;
922292SN/A
932292SN/A    /** a pointer to the system we are running in */
949915Ssteve.reinhardt@amd.com    AlphaSystem *system;
951060SN/A
961060SN/A    /** a pointer to the CPU boot cpu */
979086Sandreas.hansson@arm.com    BaseCPU *cpu;
989086Sandreas.hansson@arm.com
999086Sandreas.hansson@arm.com  public:
1009919Ssteve.reinhardt@amd.com    struct Params : public BasePioDevice::Params
1019919Ssteve.reinhardt@amd.com    {
1029919Ssteve.reinhardt@amd.com        SimConsole *cons;
1039919Ssteve.reinhardt@amd.com        SimpleDisk *disk;
1049086Sandreas.hansson@arm.com        AlphaSystem *sys;
1059915Ssteve.reinhardt@amd.com        BaseCpu *cpu;
1069915Ssteve.reinhardt@amd.com    };
1079915Ssteve.reinhardt@amd.com  protected:
1089915Ssteve.reinhardt@amd.com    const Params *params() const {return (const Params *)_params; }
1099915Ssteve.reinhardt@amd.com
1109915Ssteve.reinhardt@amd.com  public:
1119915Ssteve.reinhardt@amd.com
1129915Ssteve.reinhardt@amd.com    /** Standard Constructor */
1139915Ssteve.reinhardt@amd.com    AlphaConsole(Params *p);
1149915Ssteve.reinhardt@amd.com
1159915Ssteve.reinhardt@amd.com    virtual void startup();
1169915Ssteve.reinhardt@amd.com
1179915Ssteve.reinhardt@amd.com    /**
1189915Ssteve.reinhardt@amd.com     * memory mapped reads and writes
1199915Ssteve.reinhardt@amd.com     */
1209915Ssteve.reinhardt@amd.com    virtual Tick read(Packet &pkt);
1219915Ssteve.reinhardt@amd.com    virtual Tick write(Packet &pkt);
1229915Ssteve.reinhardt@amd.com
1239915Ssteve.reinhardt@amd.com    /**
1249915Ssteve.reinhardt@amd.com     * standard serialization routines for checkpointing
1259915Ssteve.reinhardt@amd.com     */
1269915Ssteve.reinhardt@amd.com    virtual void serialize(std::ostream &os);
1279915Ssteve.reinhardt@amd.com    virtual void unserialize(Checkpoint *cp, const std::string &section);
1289915Ssteve.reinhardt@amd.com
1299915Ssteve.reinhardt@amd.com  public:
1309915Ssteve.reinhardt@amd.com    Tick cacheAccess(MemReqPtr &req);
1319915Ssteve.reinhardt@amd.com};
1321060SN/A
1332292SN/A#endif // __ALPHA_CONSOLE_HH__
1349915Ssteve.reinhardt@amd.com