backdoor.hh revision 1804
17138Sgblack@eecs.umich.edu/* 27138Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 37138Sgblack@eecs.umich.edu * All rights reserved. 47138Sgblack@eecs.umich.edu * 57138Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67138Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77138Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97138Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117138Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127138Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137138Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147138Sgblack@eecs.umich.edu * this software without specific prior written permission. 157138Sgblack@eecs.umich.edu * 167138Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177138Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187138Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197138Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207138Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217138Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227138Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237138Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247138Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257138Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267138Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277138Sgblack@eecs.umich.edu */ 287138Sgblack@eecs.umich.edu 297138Sgblack@eecs.umich.edu/** @file 307138Sgblack@eecs.umich.edu * System Console Interface 317138Sgblack@eecs.umich.edu */ 327138Sgblack@eecs.umich.edu 337138Sgblack@eecs.umich.edu#ifndef __ALPHA_CONSOLE_HH__ 347138Sgblack@eecs.umich.edu#define __ALPHA_CONSOLE_HH__ 357138Sgblack@eecs.umich.edu 367138Sgblack@eecs.umich.edu#include "base/range.hh" 377138Sgblack@eecs.umich.edu#include "dev/alpha_access.h" 387138Sgblack@eecs.umich.edu#include "dev/io_device.hh" 397138Sgblack@eecs.umich.edu#include "sim/host.hh" 407138Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 417138Sgblack@eecs.umich.edu 427138Sgblack@eecs.umich.educlass BaseCPU; 437138Sgblack@eecs.umich.educlass SimConsole; 447138Sgblack@eecs.umich.educlass System; 457138Sgblack@eecs.umich.educlass SimpleDisk; 467214Sgblack@eecs.umich.edu 478303SAli.Saidi@ARM.com/** 487214Sgblack@eecs.umich.edu * Memory mapped interface to the system console. This device 497214Sgblack@eecs.umich.edu * represents a shared data region between the OS Kernel and the 507138Sgblack@eecs.umich.edu * System Console. 518302SAli.Saidi@ARM.com * 527138Sgblack@eecs.umich.edu * The system console is a small standalone program that is initially 537138Sgblack@eecs.umich.edu * run when the system boots. It contains the necessary code to 548305SAli.Saidi@ARM.com * access the boot disk, to read/write from the console, and to pass 558305SAli.Saidi@ARM.com * boot parameters to the kernel. 568305SAli.Saidi@ARM.com * 578305SAli.Saidi@ARM.com * This version of the system console is very different from the one 588305SAli.Saidi@ARM.com * that would be found in a real system. Many of the functions use 598305SAli.Saidi@ARM.com * some sort of backdoor to get their job done. For example, reading 608305SAli.Saidi@ARM.com * from the boot device on a real system would require a minimal 618305SAli.Saidi@ARM.com * device driver to access the disk controller, but since we have a 628305SAli.Saidi@ARM.com * simulator here, we are able to bypass the disk controller and 638305SAli.Saidi@ARM.com * access the disk image directly. There are also some things like 648305SAli.Saidi@ARM.com * reading the kernel off the disk image into memory that are normally 658305SAli.Saidi@ARM.com * taken care of by the console that are now taken care of by the 668305SAli.Saidi@ARM.com * simulator. 678305SAli.Saidi@ARM.com * 688305SAli.Saidi@ARM.com * These shortcuts are acceptable since the system console is 698305SAli.Saidi@ARM.com * primarily used doing boot before the kernel has loaded its device 708305SAli.Saidi@ARM.com * drivers. 718305SAli.Saidi@ARM.com */ 728305SAli.Saidi@ARM.comclass AlphaConsole : public PioDevice 738305SAli.Saidi@ARM.com{ 748305SAli.Saidi@ARM.com protected: 758305SAli.Saidi@ARM.com struct Access : public AlphaAccess 768305SAli.Saidi@ARM.com { 778305SAli.Saidi@ARM.com void serialize(std::ostream &os); 787138Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 797138Sgblack@eecs.umich.edu }; 808303SAli.Saidi@ARM.com 817138Sgblack@eecs.umich.edu union { 828305SAli.Saidi@ARM.com Access *alphaAccess; 838305SAli.Saidi@ARM.com uint8_t *consoleData; 847193Sgblack@eecs.umich.edu }; 857138Sgblack@eecs.umich.edu 867215Sgblack@eecs.umich.edu /** the disk must be accessed from the console */ 877138Sgblack@eecs.umich.edu SimpleDisk *disk; 887138Sgblack@eecs.umich.edu 897138Sgblack@eecs.umich.edu /** the system console (the terminal) is accessable from the console */ 907138Sgblack@eecs.umich.edu SimConsole *console; 917138Sgblack@eecs.umich.edu 927138Sgblack@eecs.umich.edu /** a pointer to the system we are running in */ 937138Sgblack@eecs.umich.edu System *system; 947138Sgblack@eecs.umich.edu 957138Sgblack@eecs.umich.edu /** a pointer to the CPU boot cpu */ 967138Sgblack@eecs.umich.edu BaseCPU *cpu; 977138Sgblack@eecs.umich.edu 987138Sgblack@eecs.umich.edu Addr addr; 997138Sgblack@eecs.umich.edu static const Addr size = 0x80; // equal to sizeof(alpha_access); 1007138Sgblack@eecs.umich.edu 1017138Sgblack@eecs.umich.edu public: 1028305SAli.Saidi@ARM.com /** Standard Constructor */ 1038305SAli.Saidi@ARM.com AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d, 1047193Sgblack@eecs.umich.edu System *s, BaseCPU *c, Platform *platform, 1057138Sgblack@eecs.umich.edu int num_cpus, MemoryController *mmu, Addr addr, 1067215Sgblack@eecs.umich.edu HierParams *hier, Bus *bus); 1077138Sgblack@eecs.umich.edu 1087138Sgblack@eecs.umich.edu virtual void init(); 1097138Sgblack@eecs.umich.edu 1108305SAli.Saidi@ARM.com /** 1117138Sgblack@eecs.umich.edu * memory mapped reads and writes 1127138Sgblack@eecs.umich.edu */ 1137138Sgblack@eecs.umich.edu virtual Fault read(MemReqPtr &req, uint8_t *data); 1147138Sgblack@eecs.umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 1158304SAli.Saidi@ARM.com 1168304SAli.Saidi@ARM.com /** 1177138Sgblack@eecs.umich.edu * standard serialization routines for checkpointing 1187193Sgblack@eecs.umich.edu */ 1197648SAli.Saidi@ARM.com virtual void serialize(std::ostream &os); 1207138Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1217138Sgblack@eecs.umich.edu 1227138Sgblack@eecs.umich.edu public: 1237138Sgblack@eecs.umich.edu Tick cacheAccess(MemReqPtr &req); 1247138Sgblack@eecs.umich.edu}; 1257193Sgblack@eecs.umich.edu 1267184Sgblack@eecs.umich.edu#endif // __ALPHA_CONSOLE_HH__ 1277214Sgblack@eecs.umich.edu