Tsunami.py revision 11244:a2af58a06c4e 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
31from BadDevice import BadDevice
32from AlphaBackdoor import AlphaBackdoor
33from Device import BasicPioDevice, IsaFake, BadAddr
34from PciHost import GenericPciHost
35from Platform import Platform
36from Uart import Uart8250
37
38class TsunamiCChip(BasicPioDevice):
39    type = 'TsunamiCChip'
40    cxx_header = "dev/alpha/tsunami_cchip.hh"
41    tsunami = Param.Tsunami(Parent.any, "Tsunami")
42
43class TsunamiIO(BasicPioDevice):
44    type = 'TsunamiIO'
45    cxx_header = "dev/alpha/tsunami_io.hh"
46    time = Param.Time('01/01/2009',
47        "System time to use ('Now' for actual time)")
48    year_is_bcd = Param.Bool(False,
49        "The RTC should interpret the year as a BCD value")
50    tsunami = Param.Tsunami(Parent.any, "Tsunami")
51    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
52
53class TsunamiPChip(GenericPciHost):
54    type = 'TsunamiPChip'
55    cxx_header = "dev/alpha/tsunami_pchip.hh"
56
57    conf_base = 0x801fe000000
58    conf_size = "16MB"
59
60    pci_pio_base = 0x801fc000000
61    pci_mem_base = 0x80000000000
62
63    pio_addr = Param.Addr("Device Address")
64    pio_latency = Param.Latency('100ns', "Programmed IO latency")
65
66    tsunami = Param.Tsunami(Parent.any, "Tsunami")
67
68class Tsunami(Platform):
69    type = 'Tsunami'
70    cxx_header = "dev/alpha/tsunami.hh"
71    system = Param.System(Parent.any, "system")
72
73    cchip = TsunamiCChip(pio_addr=0x801a0000000)
74    pchip = TsunamiPChip(pio_addr=0x80180000000)
75    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
76
77    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
78    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
79    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
80    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
81
82    fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
83
84    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
85
86    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
87    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
88    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
89    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
90    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
91    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
92    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
93    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
94    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
95    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
96
97    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
98    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
99
100    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
101    io = TsunamiIO(pio_addr=0x801fc000000)
102    uart = Uart8250(pio_addr=0x801fc0003f8)
103    backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
104
105    # Attach I/O devices to specified bus object.  Can't do this
106    # earlier, since the bus object itself is typically defined at the
107    # System level.
108    def attachIO(self, bus):
109        self.cchip.pio = bus.master
110        self.pchip.pio = bus.master
111        self.fake_sm_chip.pio = bus.master
112        self.fake_uart1.pio = bus.master
113        self.fake_uart2.pio = bus.master
114        self.fake_uart3.pio = bus.master
115        self.fake_uart4.pio = bus.master
116        self.fake_ppc.pio = bus.master
117        self.fake_OROM.pio = bus.master
118        self.fake_pnp_addr.pio = bus.master
119        self.fake_pnp_write.pio = bus.master
120        self.fake_pnp_read0.pio = bus.master
121        self.fake_pnp_read1.pio = bus.master
122        self.fake_pnp_read2.pio = bus.master
123        self.fake_pnp_read3.pio = bus.master
124        self.fake_pnp_read4.pio = bus.master
125        self.fake_pnp_read5.pio = bus.master
126        self.fake_pnp_read6.pio = bus.master
127        self.fake_pnp_read7.pio = bus.master
128        self.fake_ata0.pio = bus.master
129        self.fake_ata1.pio = bus.master
130        self.fb.pio = bus.master
131        self.io.pio = bus.master
132        self.uart.pio = bus.master
133        self.backdoor.pio = bus.master
134