Tsunami.py revision 9338
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Nathan Binkert 284486Sbinkertn@umich.edu 293102SN/Afrom m5.params import * 303102SN/Afrom m5.proxy import * 315480Snate@binkert.orgfrom BadDevice import BadDevice 325480Snate@binkert.orgfrom AlphaBackdoor import AlphaBackdoor 333812SN/Afrom Device import BasicPioDevice, IsaFake, BadAddr 345480Snate@binkert.orgfrom Pci import PciConfigAll 351310SN/Afrom Platform import Platform 362916SN/Afrom Uart import Uart8250 371310SN/A 382542SN/Aclass TsunamiCChip(BasicPioDevice): 391366SN/A type = 'TsunamiCChip' 409338SAndreas.Sandberg@arm.com cxx_header = "dev/alpha/tsunami_cchip.hh" 411692SN/A tsunami = Param.Tsunami(Parent.any, "Tsunami") 421310SN/A 432542SN/Aclass TsunamiIO(BasicPioDevice): 441366SN/A type = 'TsunamiIO' 459338SAndreas.Sandberg@arm.com cxx_header = "dev/alpha/tsunami_io.hh" 463934SN/A time = Param.Time('01/01/2009', 473885SN/A "System time to use ('Now' for actual time)") 483932SN/A year_is_bcd = Param.Bool(False, 493932SN/A "The RTC should interpret the year as a BCD value") 501692SN/A tsunami = Param.Tsunami(Parent.any, "Tsunami") 511634SN/A frequency = Param.Frequency('1024Hz', "frequency of interrupts") 521310SN/A 532542SN/Aclass TsunamiPChip(BasicPioDevice): 541366SN/A type = 'TsunamiPChip' 559338SAndreas.Sandberg@arm.com cxx_header = "dev/alpha/tsunami_pchip.hh" 561692SN/A tsunami = Param.Tsunami(Parent.any, "Tsunami") 572916SN/A 582916SN/Aclass Tsunami(Platform): 592916SN/A type = 'Tsunami' 609338SAndreas.Sandberg@arm.com cxx_header = "dev/alpha/tsunami.hh" 612916SN/A system = Param.System(Parent.any, "system") 622916SN/A 632916SN/A cchip = TsunamiCChip(pio_addr=0x801a0000000) 642916SN/A pchip = TsunamiPChip(pio_addr=0x80180000000) 652916SN/A pciconfig = PciConfigAll() 662916SN/A fake_sm_chip = IsaFake(pio_addr=0x801fc000370) 672916SN/A 682916SN/A fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) 692916SN/A fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) 702916SN/A fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) 712916SN/A fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) 722916SN/A 733847SN/A fake_ppc = IsaFake(pio_addr=0x801fc0003bb) 742916SN/A 752916SN/A fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) 762916SN/A 772916SN/A fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) 782916SN/A fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) 792916SN/A fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) 802916SN/A fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) 812916SN/A fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) 822916SN/A fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) 832916SN/A fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) 842916SN/A fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) 852916SN/A fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) 862916SN/A fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) 872916SN/A 882916SN/A fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) 892916SN/A fake_ata1 = IsaFake(pio_addr=0x801fc000170) 902916SN/A 912916SN/A fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') 922916SN/A io = TsunamiIO(pio_addr=0x801fc000000) 932916SN/A uart = Uart8250(pio_addr=0x801fc0003f8) 945480Snate@binkert.org backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) 952916SN/A 962916SN/A # Attach I/O devices to specified bus object. Can't do this 972916SN/A # earlier, since the bus object itself is typically defined at the 982916SN/A # System level. 992916SN/A def attachIO(self, bus): 1008839Sandreas.hansson@arm.com self.cchip.pio = bus.master 1018839Sandreas.hansson@arm.com self.pchip.pio = bus.master 1022916SN/A self.pciconfig.pio = bus.default 1037523Ssteve.reinhardt@amd.com bus.use_default_range = True 1048839Sandreas.hansson@arm.com self.fake_sm_chip.pio = bus.master 1058839Sandreas.hansson@arm.com self.fake_uart1.pio = bus.master 1068839Sandreas.hansson@arm.com self.fake_uart2.pio = bus.master 1078839Sandreas.hansson@arm.com self.fake_uart3.pio = bus.master 1088839Sandreas.hansson@arm.com self.fake_uart4.pio = bus.master 1098839Sandreas.hansson@arm.com self.fake_ppc.pio = bus.master 1108839Sandreas.hansson@arm.com self.fake_OROM.pio = bus.master 1118839Sandreas.hansson@arm.com self.fake_pnp_addr.pio = bus.master 1128839Sandreas.hansson@arm.com self.fake_pnp_write.pio = bus.master 1138839Sandreas.hansson@arm.com self.fake_pnp_read0.pio = bus.master 1148839Sandreas.hansson@arm.com self.fake_pnp_read1.pio = bus.master 1158839Sandreas.hansson@arm.com self.fake_pnp_read2.pio = bus.master 1168839Sandreas.hansson@arm.com self.fake_pnp_read3.pio = bus.master 1178839Sandreas.hansson@arm.com self.fake_pnp_read4.pio = bus.master 1188839Sandreas.hansson@arm.com self.fake_pnp_read5.pio = bus.master 1198839Sandreas.hansson@arm.com self.fake_pnp_read6.pio = bus.master 1208839Sandreas.hansson@arm.com self.fake_pnp_read7.pio = bus.master 1218839Sandreas.hansson@arm.com self.fake_ata0.pio = bus.master 1228839Sandreas.hansson@arm.com self.fake_ata1.pio = bus.master 1238839Sandreas.hansson@arm.com self.fb.pio = bus.master 1248839Sandreas.hansson@arm.com self.io.pio = bus.master 1258839Sandreas.hansson@arm.com self.uart.pio = bus.master 1268839Sandreas.hansson@arm.com self.backdoor.pio = bus.master 127