Tsunami.py revision 3502 
1from m5.params import *
2from m5.proxy import *
3from Device import BasicPioDevice
4from Platform import Platform
5from AlphaConsole import AlphaConsole
6from Uart import Uart8250
7from Pci import PciConfigAll
8from BadDevice import BadDevice
9
10class TsunamiCChip(BasicPioDevice):
11    type = 'TsunamiCChip'
12    tsunami = Param.Tsunami(Parent.any, "Tsunami")
13
14class IsaFake(BasicPioDevice):
15    type = 'IsaFake'
16    pio_size = Param.Addr(0x8, "Size of address range")
17    ret_data = Param.UInt8(0xFF, "Default data to return")
18    ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
19
20class BadAddr(IsaFake):
21    ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
22
23class TsunamiIO(BasicPioDevice):
24    type = 'TsunamiIO'
25    time = Param.UInt64(1136073600,
26        "System time to use (0 for actual time, default is 1/1/06)")
27    tsunami = Param.Tsunami(Parent.any, "Tsunami")
28    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
29
30class TsunamiPChip(BasicPioDevice):
31    type = 'TsunamiPChip'
32    tsunami = Param.Tsunami(Parent.any, "Tsunami")
33
34class Tsunami(Platform):
35    type = 'Tsunami'
36    system = Param.System(Parent.any, "system")
37
38    cchip = TsunamiCChip(pio_addr=0x801a0000000)
39    pchip = TsunamiPChip(pio_addr=0x80180000000)
40    pciconfig = PciConfigAll()
41    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
42
43    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
44    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
45    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
46    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
47
48    fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
49
50    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
51
52    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
53    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
54    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
55    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
56    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
57    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
58    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
59    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
60    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
61    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
62
63    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
64    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
65
66    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
67    io = TsunamiIO(pio_addr=0x801fc000000)
68    uart = Uart8250(pio_addr=0x801fc0003f8)
69    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
70
71    # Attach I/O devices to specified bus object.  Can't do this
72    # earlier, since the bus object itself is typically defined at the
73    # System level.
74    def attachIO(self, bus):
75        self.cchip.pio = bus.port
76        self.pchip.pio = bus.port
77        self.pciconfig.pio = bus.default
78        bus.responder_set = True
79        bus.responder = self.pciconfig
80        self.fake_sm_chip.pio = bus.port
81        self.fake_uart1.pio = bus.port
82        self.fake_uart2.pio = bus.port
83        self.fake_uart3.pio = bus.port
84        self.fake_uart4.pio = bus.port
85        self.fake_ppc.pio = bus.port
86        self.fake_OROM.pio = bus.port
87        self.fake_pnp_addr.pio = bus.port
88        self.fake_pnp_write.pio = bus.port
89        self.fake_pnp_read0.pio = bus.port
90        self.fake_pnp_read1.pio = bus.port
91        self.fake_pnp_read2.pio = bus.port
92        self.fake_pnp_read3.pio = bus.port
93        self.fake_pnp_read4.pio = bus.port
94        self.fake_pnp_read5.pio = bus.port
95        self.fake_pnp_read6.pio = bus.port
96        self.fake_pnp_read7.pio = bus.port
97        self.fake_ata0.pio = bus.port
98        self.fake_ata1.pio = bus.port
99        self.fb.pio = bus.port
100        self.io.pio = bus.port
101        self.uart.pio = bus.port
102        self.console.pio = bus.port
103