SConscript revision 10923
1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Steve Reinhardt 30# Gabe Black 31 32Import('*') 33 34SimObject('Device.py') 35Source('io_device.cc') 36Source('isa_fake.cc') 37DebugFlag('IsaFake') 38 39if env['TARGET_ISA'] == 'null': 40 Return() 41 42SimObject('BadDevice.py') 43SimObject('CopyEngine.py') 44SimObject('DiskImage.py') 45SimObject('Ethernet.py') 46SimObject('I2C.py') 47SimObject('Ide.py') 48SimObject('Pci.py') 49SimObject('Platform.py') 50SimObject('SimpleDisk.py') 51SimObject('Terminal.py') 52SimObject('Uart.py') 53 54Source('baddev.cc') 55Source('copy_engine.cc') 56Source('disk_image.cc') 57Source('dma_device.cc') 58Source('etherbus.cc') 59Source('etherdevice.cc') 60Source('etherdump.cc') 61Source('etherint.cc') 62Source('etherlink.cc') 63Source('multi_packet.cc') 64Source('multi_iface.cc') 65Source('multi_etherlink.cc') 66Source('tcp_iface.cc') 67Source('etherpkt.cc') 68Source('ethertap.cc') 69Source('i2cbus.cc') 70Source('i8254xGBe.cc') 71Source('ide_ctrl.cc') 72Source('ide_disk.cc') 73Source('intel_8254_timer.cc') 74Source('mc146818.cc') 75Source('ns_gige.cc') 76Source('pciconfigall.cc') 77Source('pcidev.cc') 78Source('pktfifo.cc') 79Source('platform.cc') 80Source('ps2.cc') 81Source('simple_disk.cc') 82Source('sinic.cc') 83Source('terminal.cc') 84Source('uart.cc') 85Source('uart8250.cc') 86 87DebugFlag('DiskImageRead') 88DebugFlag('DiskImageWrite') 89DebugFlag('DMA') 90DebugFlag('DMACopyEngine') 91DebugFlag('Ethernet') 92DebugFlag('MultiEthernet') 93DebugFlag('MultiEthernetPkt') 94DebugFlag('EthernetCksum') 95DebugFlag('EthernetDMA') 96DebugFlag('EthernetData') 97DebugFlag('EthernetDesc') 98DebugFlag('EthernetEEPROM') 99DebugFlag('EthernetIntr') 100DebugFlag('EthernetPIO') 101DebugFlag('EthernetSM') 102DebugFlag('IdeCtrl') 103DebugFlag('IdeDisk') 104DebugFlag('Intel8254Timer') 105DebugFlag('MC146818') 106DebugFlag('PCIDEV') 107DebugFlag('PciConfigAll') 108DebugFlag('SimpleDisk') 109DebugFlag('SimpleDiskData') 110DebugFlag('Terminal') 111DebugFlag('TerminalVerbose') 112DebugFlag('Uart') 113 114CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ]) 115CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 116 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 117 'EthernetCksum', 'EthernetEEPROM' ]) 118CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 119 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ]) 120CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ]) 121