SConscript revision 10800:c0957cf9f606 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30#          Gabe Black
31
32Import('*')
33
34SimObject('Device.py')
35Source('io_device.cc')
36Source('isa_fake.cc')
37DebugFlag('IsaFake')
38
39if env['TARGET_ISA'] == 'null':
40    Return()
41
42SimObject('BadDevice.py')
43SimObject('CopyEngine.py')
44SimObject('DiskImage.py')
45SimObject('Ethernet.py')
46SimObject('I2C.py')
47SimObject('Ide.py')
48SimObject('Pci.py')
49SimObject('Platform.py')
50SimObject('SimpleDisk.py')
51SimObject('Terminal.py')
52SimObject('Uart.py')
53
54Source('baddev.cc')
55Source('copy_engine.cc')
56Source('disk_image.cc')
57Source('dma_device.cc')
58Source('etherbus.cc')
59Source('etherdevice.cc')
60Source('etherdump.cc')
61Source('etherint.cc')
62Source('etherlink.cc')
63Source('etherpkt.cc')
64Source('ethertap.cc')
65Source('i2cbus.cc')
66Source('i8254xGBe.cc')
67Source('ide_ctrl.cc')
68Source('ide_disk.cc')
69Source('intel_8254_timer.cc')
70Source('mc146818.cc')
71Source('ns_gige.cc')
72Source('pciconfigall.cc')
73Source('pcidev.cc')
74Source('pktfifo.cc')
75Source('platform.cc')
76Source('ps2.cc')
77Source('simple_disk.cc')
78Source('sinic.cc')
79Source('terminal.cc')
80Source('uart.cc')
81Source('uart8250.cc')
82
83DebugFlag('DiskImageRead')
84DebugFlag('DiskImageWrite')
85DebugFlag('DMA')
86DebugFlag('DMACopyEngine')
87DebugFlag('Ethernet')
88DebugFlag('EthernetCksum')
89DebugFlag('EthernetDMA')
90DebugFlag('EthernetData')
91DebugFlag('EthernetDesc')
92DebugFlag('EthernetEEPROM')
93DebugFlag('EthernetIntr')
94DebugFlag('EthernetPIO')
95DebugFlag('EthernetSM')
96DebugFlag('IdeCtrl')
97DebugFlag('IdeDisk')
98DebugFlag('Intel8254Timer')
99DebugFlag('MC146818')
100DebugFlag('PCIDEV')
101DebugFlag('PciConfigAll')
102DebugFlag('SimpleDisk')
103DebugFlag('SimpleDiskData')
104DebugFlag('Terminal')
105DebugFlag('TerminalVerbose')
106DebugFlag('Uart')
107
108CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
109CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
110    'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
111    'EthernetCksum', 'EthernetEEPROM' ])
112CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
113    'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
114CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
115