Platform.py revision 12470:d5152049f316
110388SAndreas.Sandberg@ARM.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 210388SAndreas.Sandberg@ARM.com# All rights reserved. 310388SAndreas.Sandberg@ARM.com# 410388SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 510388SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 610388SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 710388SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 810388SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 910388SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 1010388SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 1110388SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 1210388SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 1310388SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 1410388SAndreas.Sandberg@ARM.com# 1510388SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1610388SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1710388SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1810388SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1910388SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2010388SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2110388SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2210388SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2310388SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2410388SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2510388SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2610388SAndreas.Sandberg@ARM.com# 2710388SAndreas.Sandberg@ARM.com# Authors: Nathan Binkert 2810388SAndreas.Sandberg@ARM.com 2910388SAndreas.Sandberg@ARM.comfrom m5.SimObject import SimObject 3010388SAndreas.Sandberg@ARM.comfrom m5.params import * 3110388SAndreas.Sandberg@ARM.comfrom m5.proxy import * 3210388SAndreas.Sandberg@ARM.comclass Platform(SimObject): 3310388SAndreas.Sandberg@ARM.com type = 'Platform' 3410388SAndreas.Sandberg@ARM.com abstract = True 3510388SAndreas.Sandberg@ARM.com cxx_header = "dev/platform.hh" 3610388SAndreas.Sandberg@ARM.com intrctrl = Param.IntrControl(Parent.any, "interrupt controller") 3710388SAndreas.Sandberg@ARM.com 3810388SAndreas.Sandberg@ARM.com # for platforms using device trees to set properties of CPU nodes 3910388SAndreas.Sandberg@ARM.com def annotateCpuDeviceNode(self, cpu, state): 4010388SAndreas.Sandberg@ARM.com pass 4110388SAndreas.Sandberg@ARM.com