Device.py revision 9162:019047ead23b
16145SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 28688SN/A# All rights reserved. 36145SN/A# 46145SN/A# Redistribution and use in source and binary forms, with or without 56145SN/A# modification, are permitted provided that the following conditions are 66145SN/A# met: redistributions of source code must retain the above copyright 76145SN/A# notice, this list of conditions and the following disclaimer; 86145SN/A# redistributions in binary form must reproduce the above copyright 96145SN/A# notice, this list of conditions and the following disclaimer in the 106145SN/A# documentation and/or other materials provided with the distribution; 116145SN/A# neither the name of the copyright holders nor the names of its 126145SN/A# contributors may be used to endorse or promote products derived from 136145SN/A# this software without specific prior written permission. 146145SN/A# 156145SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166145SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176145SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186145SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196145SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206145SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216145SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226145SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236145SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246145SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256145SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266145SN/A# 276145SN/A# Authors: Nathan Binkert 286145SN/A 296145SN/Afrom m5.params import * 307039SN/Afrom m5.proxy import * 317039SN/Afrom MemObject import MemObject 327039SN/A 336145SN/Aclass PioDevice(MemObject): 346145SN/A type = 'PioDevice' 357039SN/A abstract = True 367039SN/A pio = SlavePort("Programmed I/O port") 376145SN/A system = Param.System(Parent.any, "System this device is part of") 387039SN/A 399350SN/Aclass BasicPioDevice(PioDevice): 4011108Sdavid.hashe@amd.com type = 'BasicPioDevice' 4110301SN/A abstract = True 4210301SN/A pio_addr = Param.Addr("Device Address") 4310301SN/A pio_latency = Param.Latency('1ns', "Programmed IO latency") 447039SN/A 459206SN/Aclass DmaDevice(PioDevice): 466145SN/A type = 'DmaDevice' 477039SN/A abstract = True 4810920SN/A dma = MasterPort("DMA port") 496285SN/A min_backoff_delay = Param.Latency('4ns', 509206SN/A "min time between a nack packet being received and the next request made by the device") 517039SN/A max_backoff_delay = Param.Latency('10us', 527039SN/A "max time between a nack packet being received and the next request made by the device") 538688SN/A 548688SN/A 558688SN/A 568688SN/Aclass IsaFake(BasicPioDevice): 578688SN/A type = 'IsaFake' 5810919SN/A pio_size = Param.Addr(0x8, "Size of address range") 598688SN/A ret_data8 = Param.UInt8(0xFF, "Default data to return") 608688SN/A ret_data16 = Param.UInt16(0xFFFF, "Default data to return") 618688SN/A ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") 628688SN/A ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") 6310919SN/A ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 648688SN/A update_data = Param.Bool(False, "Update the data that is returned on writes") 658688SN/A warn_access = Param.String("", "String to print when device is accessed") 668688SN/A fake_mem = Param.Bool(False, 678688SN/A "Is this device acting like a memory and thus may get a cache line sized req") 686876SN/A 696876SN/Aclass BadAddr(IsaFake): 707039SN/A pio_addr = 0 716145SN/A ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") 727039SN/A 737039SN/A 749504SN/A