Device.py revision 13930:c5e728ccd2e2
1# Copyright (c) 2012-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2005-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Nathan Binkert 40# Glenn Bergmans 41 42from m5.params import * 43from m5.proxy import * 44from m5.util.fdthelper import * 45 46from m5.objects.ClockedObject import ClockedObject 47 48class PioDevice(ClockedObject): 49 type = 'PioDevice' 50 cxx_header = "dev/io_device.hh" 51 abstract = True 52 pio = SlavePort("Programmed I/O port") 53 system = Param.System(Parent.any, "System this device is part of") 54 55 def generateBasicPioDeviceNode(self, state, name, pio_addr, 56 size, interrupts = None): 57 node = FdtNode("%s@%x" % (name, long(pio_addr))) 58 node.append(FdtPropertyWords("reg", 59 state.addrCells(pio_addr) + 60 state.sizeCells(size) )) 61 62 if interrupts: 63 if any([i < 32 for i in interrupts]): 64 raise(("Interrupt number smaller than 32 "+ 65 " in PioDevice %s") % name) 66 67 # subtracting 32 because Linux assumes that SPIs start at 0, while 68 # gem5 uses the internal GIC numbering (SPIs start at 32) 69 node.append(FdtPropertyWords("interrupts", sum( 70 [[0, i - 32, 4] for i in interrupts], []) )) 71 72 return node 73 74class BasicPioDevice(PioDevice): 75 type = 'BasicPioDevice' 76 cxx_header = "dev/io_device.hh" 77 abstract = True 78 pio_addr = Param.Addr("Device Address") 79 pio_latency = Param.Latency('100ns', "Programmed IO latency") 80 81class DmaDevice(PioDevice): 82 type = 'DmaDevice' 83 cxx_header = "dev/dma_device.hh" 84 abstract = True 85 dma = MasterPort("DMA port") 86 87 sid = Param.Unsigned(0, 88 "Stream identifier used by an IOMMU to distinguish amongst " 89 "several devices attached to it") 90 ssid = Param.Unsigned(0, 91 "Substream identifier used by an IOMMU to distinguish amongst " 92 "several devices attached to it") 93 94 95class IsaFake(BasicPioDevice): 96 type = 'IsaFake' 97 cxx_header = "dev/isa_fake.hh" 98 pio_size = Param.Addr(0x8, "Size of address range") 99 ret_data8 = Param.UInt8(0xFF, "Default data to return") 100 ret_data16 = Param.UInt16(0xFFFF, "Default data to return") 101 ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") 102 ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") 103 ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 104 update_data = Param.Bool(False, "Update the data that is returned on writes") 105 warn_access = Param.String("", "String to print when device is accessed") 106 fake_mem = Param.Bool(False, 107 "Is this device acting like a memory and thus may get a cache line sized req") 108 109class BadAddr(IsaFake): 110 pio_addr = 0 111 ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") 112 113 114