TraceCPU.py revision 11631
111631Sradhika.jagtap@arm.com# Copyright (c) 2013 - 2016 ARM Limited 211249Sradhika.jagtap@ARM.com# All rights reserved. 311249Sradhika.jagtap@ARM.com# 411249Sradhika.jagtap@ARM.com# The license below extends only to copyright in the software and shall 511249Sradhika.jagtap@ARM.com# not be construed as granting a license to any other intellectual 611249Sradhika.jagtap@ARM.com# property including but not limited to intellectual property relating 711249Sradhika.jagtap@ARM.com# to a hardware implementation of the functionality of the software 811249Sradhika.jagtap@ARM.com# licensed hereunder. You may use the software subject to the license 911249Sradhika.jagtap@ARM.com# terms below provided that you ensure that this notice is replicated 1011249Sradhika.jagtap@ARM.com# unmodified and in its entirety in all distributions of the software, 1111249Sradhika.jagtap@ARM.com# modified or unmodified, in source code or in binary form. 1211249Sradhika.jagtap@ARM.com# 1311249Sradhika.jagtap@ARM.com# Redistribution and use in source and binary forms, with or without 1411249Sradhika.jagtap@ARM.com# modification, are permitted provided that the following conditions are 1511249Sradhika.jagtap@ARM.com# met: redistributions of source code must retain the above copyright 1611249Sradhika.jagtap@ARM.com# notice, this list of conditions and the following disclaimer; 1711249Sradhika.jagtap@ARM.com# redistributions in binary form must reproduce the above copyright 1811249Sradhika.jagtap@ARM.com# notice, this list of conditions and the following disclaimer in the 1911249Sradhika.jagtap@ARM.com# documentation and/or other materials provided with the distribution; 2011249Sradhika.jagtap@ARM.com# neither the name of the copyright holders nor the names of its 2111249Sradhika.jagtap@ARM.com# contributors may be used to endorse or promote products derived from 2211249Sradhika.jagtap@ARM.com# this software without specific prior written permission. 2311249Sradhika.jagtap@ARM.com# 2411249Sradhika.jagtap@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511249Sradhika.jagtap@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611249Sradhika.jagtap@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711249Sradhika.jagtap@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811249Sradhika.jagtap@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911249Sradhika.jagtap@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011249Sradhika.jagtap@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111249Sradhika.jagtap@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211249Sradhika.jagtap@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311249Sradhika.jagtap@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411249Sradhika.jagtap@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511249Sradhika.jagtap@ARM.com# 3611249Sradhika.jagtap@ARM.com# Authors: Radhika Jagtap 3711249Sradhika.jagtap@ARM.com# Andreas Hansson 3811249Sradhika.jagtap@ARM.com# Thomas Grass 3911249Sradhika.jagtap@ARM.com 4011249Sradhika.jagtap@ARM.comfrom m5.params import * 4111249Sradhika.jagtap@ARM.comfrom BaseCPU import BaseCPU 4211249Sradhika.jagtap@ARM.com 4311249Sradhika.jagtap@ARM.comclass TraceCPU(BaseCPU): 4411249Sradhika.jagtap@ARM.com """Trace CPU model which replays traces generated in a prior simulation 4511249Sradhika.jagtap@ARM.com using DerivO3CPU or its derived classes. It interfaces with L1 caches. 4611249Sradhika.jagtap@ARM.com """ 4711249Sradhika.jagtap@ARM.com type = 'TraceCPU' 4811249Sradhika.jagtap@ARM.com cxx_header = "cpu/trace/trace_cpu.hh" 4911249Sradhika.jagtap@ARM.com 5011249Sradhika.jagtap@ARM.com @classmethod 5111249Sradhika.jagtap@ARM.com def memory_mode(cls): 5211249Sradhika.jagtap@ARM.com return 'timing' 5311249Sradhika.jagtap@ARM.com 5411249Sradhika.jagtap@ARM.com @classmethod 5511249Sradhika.jagtap@ARM.com def require_caches(cls): 5611249Sradhika.jagtap@ARM.com return True 5711249Sradhika.jagtap@ARM.com 5811249Sradhika.jagtap@ARM.com def addPMU(self, pmu = None): 5911249Sradhika.jagtap@ARM.com pass 6011249Sradhika.jagtap@ARM.com 6111249Sradhika.jagtap@ARM.com @classmethod 6211249Sradhika.jagtap@ARM.com def support_take_over(cls): 6311249Sradhika.jagtap@ARM.com return True 6411249Sradhika.jagtap@ARM.com 6511249Sradhika.jagtap@ARM.com instTraceFile = Param.String("", "Instruction trace file") 6611249Sradhika.jagtap@ARM.com dataTraceFile = Param.String("", "Data dependency trace file") 6711249Sradhika.jagtap@ARM.com sizeStoreBuffer = Param.Unsigned(16, "Number of entries in the store "\ 6811249Sradhika.jagtap@ARM.com "buffer") 6911249Sradhika.jagtap@ARM.com sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer") 7011249Sradhika.jagtap@ARM.com sizeROB = Param.Unsigned(40, "Number of entries in the re-order buffer") 7111249Sradhika.jagtap@ARM.com 7211631Sradhika.jagtap@arm.com # Frequency multiplier used to effectively scale the Trace CPU frequency 7311631Sradhika.jagtap@arm.com # either up or down. Note that the Trace CPU's clock domain must also be 7411631Sradhika.jagtap@arm.com # changed when frequency is scaled. A default value of 1.0 means the same 7511631Sradhika.jagtap@arm.com # frequency as was used for generating the traces. 7611631Sradhika.jagtap@arm.com freqMultiplier = Param.Float(1.0, "Multiplier scale the Trace CPU "\ 7711631Sradhika.jagtap@arm.com "frequency up or down") 78