thread_state.hh revision 6658
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_STATE_HH__ 32#define __CPU_THREAD_STATE_HH__ 33 34#include "arch/types.hh" 35#include "config/the_isa.hh" 36#include "cpu/profile.hh" 37#include "cpu/thread_context.hh" 38#include "cpu/base.hh" 39 40#if !FULL_SYSTEM 41#include "mem/mem_object.hh" 42#include "sim/process.hh" 43#endif 44 45#if FULL_SYSTEM 46class EndQuiesceEvent; 47class FunctionProfile; 48class ProfileNode; 49namespace TheISA { 50 namespace Kernel { 51 class Statistics; 52 }; 53}; 54#endif 55 56class Checkpoint; 57class Port; 58class TranslatingPort; 59 60/** 61 * Struct for holding general thread state that is needed across CPU 62 * models. This includes things such as pointers to the process, 63 * memory, quiesce events, and certain stats. This can be expanded 64 * to hold more thread-specific stats within it. 65 */ 66struct ThreadState { 67 typedef ThreadContext::Status Status; 68 69#if FULL_SYSTEM 70 ThreadState(BaseCPU *cpu, ThreadID _tid); 71#else 72 ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process); 73#endif 74 75 ~ThreadState(); 76 77 void serialize(std::ostream &os); 78 79 void unserialize(Checkpoint *cp, const std::string §ion); 80 81 int cpuId() { return baseCpu->cpuId(); } 82 83 int contextId() { return _contextId; } 84 85 void setContextId(int id) { _contextId = id; } 86 87 void setThreadId(ThreadID id) { _threadId = id; } 88 89 ThreadID threadId() { return _threadId; } 90 91 Tick readLastActivate() { return lastActivate; } 92 93 Tick readLastSuspend() { return lastSuspend; } 94 95#if FULL_SYSTEM 96 void connectMemPorts(ThreadContext *tc); 97 98 void connectPhysPort(); 99 100 void connectVirtPort(ThreadContext *tc); 101 102 void dumpFuncProfile(); 103 104 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 105 106 void profileClear(); 107 108 void profileSample(); 109 110 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 111 112 FunctionalPort *getPhysPort() { return physPort; } 113 114 void setPhysPort(FunctionalPort *port) { physPort = port; } 115 116 VirtualPort *getVirtPort() { return virtPort; } 117#else 118 Process *getProcessPtr() { return process; } 119 120 TranslatingPort *getMemPort(); 121 122 void setMemPort(TranslatingPort *_port) { port = _port; } 123#endif 124 125 /** Sets the current instruction being committed. */ 126 void setInst(TheISA::MachInst _inst) { inst = _inst; } 127 128 /** Returns the current instruction being committed. */ 129 TheISA::MachInst getInst() { return inst; } 130 131 /** Reads the number of instructions functionally executed and 132 * committed. 133 */ 134 Counter readFuncExeInst() { return funcExeInst; } 135 136 /** Sets the total number of instructions functionally executed 137 * and committed. 138 */ 139 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 140 141 /** Returns the status of this thread. */ 142 Status status() const { return _status; } 143 144 /** Sets the status of this thread. */ 145 void setStatus(Status new_status) { _status = new_status; } 146 147 public: 148 /** Connects port to the functional port of the memory object 149 * below the CPU. */ 150 void connectToMemFunc(Port *port); 151 152 /** Number of instructions committed. */ 153 Counter numInst; 154 /** Stat for number instructions committed. */ 155 Stats::Scalar numInsts; 156 /** Stat for number of memory references. */ 157 Stats::Scalar numMemRefs; 158 159 /** Number of simulated loads, used for tracking events based on 160 * the number of loads committed. 161 */ 162 Counter numLoad; 163 164 /** The number of simulated loads committed prior to this run. */ 165 Counter startNumLoad; 166 167 protected: 168 ThreadContext::Status _status; 169 170 // Pointer to the base CPU. 171 BaseCPU *baseCpu; 172 173 // system wide HW context id 174 int _contextId; 175 176 // Index of hardware thread context on the CPU that this represents. 177 ThreadID _threadId; 178 179 public: 180 /** Last time activate was called on this thread. */ 181 Tick lastActivate; 182 183 /** Last time suspend was called on this thread. */ 184 Tick lastSuspend; 185 186#if FULL_SYSTEM 187 public: 188 FunctionProfile *profile; 189 ProfileNode *profileNode; 190 Addr profilePC; 191 EndQuiesceEvent *quiesceEvent; 192 193 TheISA::Kernel::Statistics *kernelStats; 194 protected: 195 /** A functional port outgoing only for functional accesses to physical 196 * addresses.*/ 197 FunctionalPort *physPort; 198 199 /** A functional port, outgoing only, for functional accesse to virtual 200 * addresses. */ 201 VirtualPort *virtPort; 202#else 203 TranslatingPort *port; 204 205 Process *process; 206#endif 207 208 /** Current instruction the thread is committing. Only set and 209 * used for DTB faults currently. 210 */ 211 TheISA::MachInst inst; 212 213 public: 214 /** 215 * Temporary storage to pass the source address from copy_load to 216 * copy_store. 217 * @todo Remove this temporary when we have a better way to do it. 218 */ 219 Addr copySrcAddr; 220 /** 221 * Temp storage for the physical source address of a copy. 222 * @todo Remove this temporary when we have a better way to do it. 223 */ 224 Addr copySrcPhysAddr; 225 226 /* 227 * number of executed instructions, for matching with syscall trace 228 * points in EIO files. 229 */ 230 Counter funcExeInst; 231 232 // 233 // Count failed store conditionals so we can warn of apparent 234 // application deadlock situations. 235 unsigned storeCondFailures; 236}; 237 238#endif // __CPU_THREAD_STATE_HH__ 239