thread_state.hh revision 5714
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_STATE_HH__ 32#define __CPU_THREAD_STATE_HH__ 33 34#include "arch/types.hh" 35#include "cpu/profile.hh" 36#include "cpu/thread_context.hh" 37#include "cpu/base.hh" 38 39#if !FULL_SYSTEM 40#include "mem/mem_object.hh" 41#include "sim/process.hh" 42#endif 43 44#if FULL_SYSTEM 45class EndQuiesceEvent; 46class FunctionProfile; 47class ProfileNode; 48namespace TheISA { 49 namespace Kernel { 50 class Statistics; 51 }; 52}; 53#endif 54 55class Checkpoint; 56class Port; 57class TranslatingPort; 58 59/** 60 * Struct for holding general thread state that is needed across CPU 61 * models. This includes things such as pointers to the process, 62 * memory, quiesce events, and certain stats. This can be expanded 63 * to hold more thread-specific stats within it. 64 */ 65struct ThreadState { 66 typedef ThreadContext::Status Status; 67 68#if FULL_SYSTEM 69 ThreadState(BaseCPU *cpu, int _tid); 70#else 71 ThreadState(BaseCPU *cpu, int _tid, Process *_process, 72 short _asid); 73#endif 74 75 ~ThreadState(); 76 77 void serialize(std::ostream &os); 78 79 void unserialize(Checkpoint *cp, const std::string §ion); 80 81 int cpuId() { return baseCpu->cpuId(); } 82 83 int contextId() { return _contextId; } 84 85 void setContextId(int id) { _contextId = id; } 86 87 void setTid(int id) { tid = id; } 88 89 int readTid() { return tid; } 90 91 Tick readLastActivate() { return lastActivate; } 92 93 Tick readLastSuspend() { return lastSuspend; } 94 95#if FULL_SYSTEM 96 void connectMemPorts(ThreadContext *tc); 97 98 void connectPhysPort(); 99 100 void connectVirtPort(ThreadContext *tc); 101 102 void dumpFuncProfile(); 103 104 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 105 106 void profileClear(); 107 108 void profileSample(); 109 110 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 111 112 FunctionalPort *getPhysPort() { return physPort; } 113 114 void setPhysPort(FunctionalPort *port) { physPort = port; } 115 116 VirtualPort *getVirtPort() { return virtPort; } 117#else 118 Process *getProcessPtr() { return process; } 119 120 TranslatingPort *getMemPort(); 121 122 void setMemPort(TranslatingPort *_port) { port = _port; } 123 124 int getInstAsid() { return asid; } 125 int getDataAsid() { return asid; } 126#endif 127 128 /** Sets the current instruction being committed. */ 129 void setInst(TheISA::MachInst _inst) { inst = _inst; } 130 131 /** Returns the current instruction being committed. */ 132 TheISA::MachInst getInst() { return inst; } 133 134 /** Reads the number of instructions functionally executed and 135 * committed. 136 */ 137 Counter readFuncExeInst() { return funcExeInst; } 138 139 /** Sets the total number of instructions functionally executed 140 * and committed. 141 */ 142 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 143 144 /** Returns the status of this thread. */ 145 Status status() const { return _status; } 146 147 /** Sets the status of this thread. */ 148 void setStatus(Status new_status) { _status = new_status; } 149 150 public: 151 /** Connects port to the functional port of the memory object 152 * below the CPU. */ 153 void connectToMemFunc(Port *port); 154 155 /** Number of instructions committed. */ 156 Counter numInst; 157 /** Stat for number instructions committed. */ 158 Stats::Scalar<> numInsts; 159 /** Stat for number of memory references. */ 160 Stats::Scalar<> numMemRefs; 161 162 /** Number of simulated loads, used for tracking events based on 163 * the number of loads committed. 164 */ 165 Counter numLoad; 166 167 /** The number of simulated loads committed prior to this run. */ 168 Counter startNumLoad; 169 170 protected: 171 ThreadContext::Status _status; 172 173 // Pointer to the base CPU. 174 BaseCPU *baseCpu; 175 176 // system wide HW context id 177 int _contextId; 178 179 // Index of hardware thread context on the CPU that this represents. 180 int tid; 181 182 public: 183 /** Last time activate was called on this thread. */ 184 Tick lastActivate; 185 186 /** Last time suspend was called on this thread. */ 187 Tick lastSuspend; 188 189#if FULL_SYSTEM 190 public: 191 FunctionProfile *profile; 192 ProfileNode *profileNode; 193 Addr profilePC; 194 EndQuiesceEvent *quiesceEvent; 195 196 TheISA::Kernel::Statistics *kernelStats; 197 protected: 198 /** A functional port outgoing only for functional accesses to physical 199 * addresses.*/ 200 FunctionalPort *physPort; 201 202 /** A functional port, outgoing only, for functional accesse to virtual 203 * addresses. */ 204 VirtualPort *virtPort; 205#else 206 TranslatingPort *port; 207 208 Process *process; 209 210 // Address space ID. Note that this is used for TIMING cache 211 // simulation only; all functional memory accesses should use 212 // one of the FunctionalMemory pointers above. 213 short asid; 214 215#endif 216 217 /** Current instruction the thread is committing. Only set and 218 * used for DTB faults currently. 219 */ 220 TheISA::MachInst inst; 221 222 /** The current microcode pc for the currently executing macro 223 * operation. 224 */ 225 MicroPC microPC; 226 227 /** The next microcode pc for the currently executing macro 228 * operation. 229 */ 230 MicroPC nextMicroPC; 231 232 public: 233 /** 234 * Temporary storage to pass the source address from copy_load to 235 * copy_store. 236 * @todo Remove this temporary when we have a better way to do it. 237 */ 238 Addr copySrcAddr; 239 /** 240 * Temp storage for the physical source address of a copy. 241 * @todo Remove this temporary when we have a better way to do it. 242 */ 243 Addr copySrcPhysAddr; 244 245 /* 246 * number of executed instructions, for matching with syscall trace 247 * points in EIO files. 248 */ 249 Counter funcExeInst; 250 251 // 252 // Count failed store conditionals so we can warn of apparent 253 // application deadlock situations. 254 unsigned storeCondFailures; 255}; 256 257#endif // __CPU_THREAD_STATE_HH__ 258