thread_state.hh revision 5712
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_STATE_HH__ 32#define __CPU_THREAD_STATE_HH__ 33 34#include "arch/types.hh" 35#include "cpu/profile.hh" 36#include "cpu/thread_context.hh" 37#include "cpu/base.hh" 38 39#if !FULL_SYSTEM 40#include "mem/mem_object.hh" 41#include "sim/process.hh" 42#endif 43 44#if FULL_SYSTEM 45class EndQuiesceEvent; 46class FunctionProfile; 47class ProfileNode; 48namespace TheISA { 49 namespace Kernel { 50 class Statistics; 51 }; 52}; 53#endif 54 55class Checkpoint; 56class Port; 57class TranslatingPort; 58 59/** 60 * Struct for holding general thread state that is needed across CPU 61 * models. This includes things such as pointers to the process, 62 * memory, quiesce events, and certain stats. This can be expanded 63 * to hold more thread-specific stats within it. 64 */ 65struct ThreadState { 66 typedef ThreadContext::Status Status; 67 68#if FULL_SYSTEM 69 ThreadState(BaseCPU *cpu, int _tid); 70#else 71 ThreadState(BaseCPU *cpu, int _tid, Process *_process, 72 short _asid); 73#endif 74 75 ~ThreadState(); 76 77 void serialize(std::ostream &os); 78 79 void unserialize(Checkpoint *cp, const std::string §ion); 80 81 int cpuId() { return baseCpu->cpuId(); } 82 83 void setTid(int id) { tid = id; } 84 85 int readTid() { return tid; } 86 87 Tick readLastActivate() { return lastActivate; } 88 89 Tick readLastSuspend() { return lastSuspend; } 90 91#if FULL_SYSTEM 92 void connectMemPorts(ThreadContext *tc); 93 94 void connectPhysPort(); 95 96 void connectVirtPort(ThreadContext *tc); 97 98 void dumpFuncProfile(); 99 100 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 101 102 void profileClear(); 103 104 void profileSample(); 105 106 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 107 108 FunctionalPort *getPhysPort() { return physPort; } 109 110 void setPhysPort(FunctionalPort *port) { physPort = port; } 111 112 VirtualPort *getVirtPort() { return virtPort; } 113#else 114 Process *getProcessPtr() { return process; } 115 116 TranslatingPort *getMemPort(); 117 118 void setMemPort(TranslatingPort *_port) { port = _port; } 119 120 int getInstAsid() { return asid; } 121 int getDataAsid() { return asid; } 122#endif 123 124 /** Sets the current instruction being committed. */ 125 void setInst(TheISA::MachInst _inst) { inst = _inst; } 126 127 /** Returns the current instruction being committed. */ 128 TheISA::MachInst getInst() { return inst; } 129 130 /** Reads the number of instructions functionally executed and 131 * committed. 132 */ 133 Counter readFuncExeInst() { return funcExeInst; } 134 135 /** Sets the total number of instructions functionally executed 136 * and committed. 137 */ 138 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 139 140 /** Returns the status of this thread. */ 141 Status status() const { return _status; } 142 143 /** Sets the status of this thread. */ 144 void setStatus(Status new_status) { _status = new_status; } 145 146 public: 147 /** Connects port to the functional port of the memory object 148 * below the CPU. */ 149 void connectToMemFunc(Port *port); 150 151 /** Number of instructions committed. */ 152 Counter numInst; 153 /** Stat for number instructions committed. */ 154 Stats::Scalar<> numInsts; 155 /** Stat for number of memory references. */ 156 Stats::Scalar<> numMemRefs; 157 158 /** Number of simulated loads, used for tracking events based on 159 * the number of loads committed. 160 */ 161 Counter numLoad; 162 163 /** The number of simulated loads committed prior to this run. */ 164 Counter startNumLoad; 165 166 protected: 167 ThreadContext::Status _status; 168 169 // Pointer to the base CPU. 170 BaseCPU *baseCpu; 171 172 // Index of hardware thread context on the CPU that this represents. 173 int tid; 174 175 public: 176 /** Last time activate was called on this thread. */ 177 Tick lastActivate; 178 179 /** Last time suspend was called on this thread. */ 180 Tick lastSuspend; 181 182#if FULL_SYSTEM 183 public: 184 FunctionProfile *profile; 185 ProfileNode *profileNode; 186 Addr profilePC; 187 EndQuiesceEvent *quiesceEvent; 188 189 TheISA::Kernel::Statistics *kernelStats; 190 protected: 191 /** A functional port outgoing only for functional accesses to physical 192 * addresses.*/ 193 FunctionalPort *physPort; 194 195 /** A functional port, outgoing only, for functional accesse to virtual 196 * addresses. */ 197 VirtualPort *virtPort; 198#else 199 TranslatingPort *port; 200 201 Process *process; 202 203 // Address space ID. Note that this is used for TIMING cache 204 // simulation only; all functional memory accesses should use 205 // one of the FunctionalMemory pointers above. 206 short asid; 207 208#endif 209 210 /** Current instruction the thread is committing. Only set and 211 * used for DTB faults currently. 212 */ 213 TheISA::MachInst inst; 214 215 /** The current microcode pc for the currently executing macro 216 * operation. 217 */ 218 MicroPC microPC; 219 220 /** The next microcode pc for the currently executing macro 221 * operation. 222 */ 223 MicroPC nextMicroPC; 224 225 public: 226 /** 227 * Temporary storage to pass the source address from copy_load to 228 * copy_store. 229 * @todo Remove this temporary when we have a better way to do it. 230 */ 231 Addr copySrcAddr; 232 /** 233 * Temp storage for the physical source address of a copy. 234 * @todo Remove this temporary when we have a better way to do it. 235 */ 236 Addr copySrcPhysAddr; 237 238 /* 239 * number of executed instructions, for matching with syscall trace 240 * points in EIO files. 241 */ 242 Counter funcExeInst; 243 244 // 245 // Count failed store conditionals so we can warn of apparent 246 // application deadlock situations. 247 unsigned storeCondFailures; 248}; 249 250#endif // __CPU_THREAD_STATE_HH__ 251