thread_state.hh revision 5499
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_STATE_HH__ 32#define __CPU_THREAD_STATE_HH__ 33 34#include "arch/types.hh" 35#include "cpu/profile.hh" 36#include "cpu/thread_context.hh" 37 38#if !FULL_SYSTEM 39#include "mem/mem_object.hh" 40#include "sim/process.hh" 41#endif 42 43#if FULL_SYSTEM 44class EndQuiesceEvent; 45class FunctionProfile; 46class ProfileNode; 47namespace TheISA { 48 namespace Kernel { 49 class Statistics; 50 }; 51}; 52#endif 53 54class BaseCPU; 55class Checkpoint; 56class Port; 57class TranslatingPort; 58 59/** 60 * Struct for holding general thread state that is needed across CPU 61 * models. This includes things such as pointers to the process, 62 * memory, quiesce events, and certain stats. This can be expanded 63 * to hold more thread-specific stats within it. 64 */ 65struct ThreadState { 66 typedef ThreadContext::Status Status; 67 68#if FULL_SYSTEM 69 ThreadState(BaseCPU *cpu, int _cpuId, int _tid); 70#else 71 ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 72 short _asid); 73#endif 74 75 ~ThreadState(); 76 77 void serialize(std::ostream &os); 78 79 void unserialize(Checkpoint *cp, const std::string §ion); 80 81 void setCpuId(int id) { cpuId = id; } 82 83 int readCpuId() { return cpuId; } 84 85 void setTid(int id) { tid = id; } 86 87 int readTid() { return tid; } 88 89 Tick readLastActivate() { return lastActivate; } 90 91 Tick readLastSuspend() { return lastSuspend; } 92 93#if FULL_SYSTEM 94 void connectMemPorts(ThreadContext *tc); 95 96 void connectPhysPort(); 97 98 void connectVirtPort(ThreadContext *tc); 99 100 void dumpFuncProfile(); 101 102 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 103 104 void profileClear(); 105 106 void profileSample(); 107 108 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 109 110 FunctionalPort *getPhysPort() { return physPort; } 111 112 void setPhysPort(FunctionalPort *port) { physPort = port; } 113 114 VirtualPort *getVirtPort() { return virtPort; } 115#else 116 Process *getProcessPtr() { return process; } 117 118 TranslatingPort *getMemPort(); 119 120 void setMemPort(TranslatingPort *_port) { port = _port; } 121 122 int getInstAsid() { return asid; } 123 int getDataAsid() { return asid; } 124#endif 125 126 /** Sets the current instruction being committed. */ 127 void setInst(TheISA::MachInst _inst) { inst = _inst; } 128 129 /** Returns the current instruction being committed. */ 130 TheISA::MachInst getInst() { return inst; } 131 132 /** Reads the number of instructions functionally executed and 133 * committed. 134 */ 135 Counter readFuncExeInst() { return funcExeInst; } 136 137 /** Sets the total number of instructions functionally executed 138 * and committed. 139 */ 140 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 141 142 /** Returns the status of this thread. */ 143 Status status() const { return _status; } 144 145 /** Sets the status of this thread. */ 146 void setStatus(Status new_status) { _status = new_status; } 147 148 public: 149 /** Connects port to the functional port of the memory object 150 * below the CPU. */ 151 void connectToMemFunc(Port *port); 152 153 /** Number of instructions committed. */ 154 Counter numInst; 155 /** Stat for number instructions committed. */ 156 Stats::Scalar<> numInsts; 157 /** Stat for number of memory references. */ 158 Stats::Scalar<> numMemRefs; 159 160 /** Number of simulated loads, used for tracking events based on 161 * the number of loads committed. 162 */ 163 Counter numLoad; 164 165 /** The number of simulated loads committed prior to this run. */ 166 Counter startNumLoad; 167 168 protected: 169 ThreadContext::Status _status; 170 171 // Pointer to the base CPU. 172 BaseCPU *baseCpu; 173 174 // ID of this context w.r.t. the System or Process object to which 175 // it belongs. For full-system mode, this is the system CPU ID. 176 int cpuId; 177 178 // Index of hardware thread context on the CPU that this represents. 179 int tid; 180 181 public: 182 /** Last time activate was called on this thread. */ 183 Tick lastActivate; 184 185 /** Last time suspend was called on this thread. */ 186 Tick lastSuspend; 187 188#if FULL_SYSTEM 189 public: 190 FunctionProfile *profile; 191 ProfileNode *profileNode; 192 Addr profilePC; 193 EndQuiesceEvent *quiesceEvent; 194 195 TheISA::Kernel::Statistics *kernelStats; 196 protected: 197 /** A functional port outgoing only for functional accesses to physical 198 * addresses.*/ 199 FunctionalPort *physPort; 200 201 /** A functional port, outgoing only, for functional accesse to virtual 202 * addresses. */ 203 VirtualPort *virtPort; 204#else 205 TranslatingPort *port; 206 207 Process *process; 208 209 // Address space ID. Note that this is used for TIMING cache 210 // simulation only; all functional memory accesses should use 211 // one of the FunctionalMemory pointers above. 212 short asid; 213 214#endif 215 216 /** Current instruction the thread is committing. Only set and 217 * used for DTB faults currently. 218 */ 219 TheISA::MachInst inst; 220 221 /** The current microcode pc for the currently executing macro 222 * operation. 223 */ 224 MicroPC microPC; 225 226 /** The next microcode pc for the currently executing macro 227 * operation. 228 */ 229 MicroPC nextMicroPC; 230 231 public: 232 /** 233 * Temporary storage to pass the source address from copy_load to 234 * copy_store. 235 * @todo Remove this temporary when we have a better way to do it. 236 */ 237 Addr copySrcAddr; 238 /** 239 * Temp storage for the physical source address of a copy. 240 * @todo Remove this temporary when we have a better way to do it. 241 */ 242 Addr copySrcPhysAddr; 243 244 /* 245 * number of executed instructions, for matching with syscall trace 246 * points in EIO files. 247 */ 248 Counter funcExeInst; 249 250 // 251 // Count failed store conditionals so we can warn of apparent 252 // application deadlock situations. 253 unsigned storeCondFailures; 254}; 255 256#endif // __CPU_THREAD_STATE_HH__ 257