thread_state.hh revision 3673
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_STATE_HH__ 32#define __CPU_THREAD_STATE_HH__ 33 34#include "arch/types.hh" 35#include "cpu/profile.hh" 36#include "cpu/thread_context.hh" 37 38#if !FULL_SYSTEM 39#include "mem/mem_object.hh" 40#include "sim/process.hh" 41#endif 42 43#if FULL_SYSTEM 44class EndQuiesceEvent; 45class FunctionProfile; 46class ProfileNode; 47namespace TheISA { 48 namespace Kernel { 49 class Statistics; 50 }; 51}; 52#endif 53 54class BaseCPU; 55class Checkpoint; 56class Port; 57class TranslatingPort; 58 59/** 60 * Struct for holding general thread state that is needed across CPU 61 * models. This includes things such as pointers to the process, 62 * memory, quiesce events, and certain stats. This can be expanded 63 * to hold more thread-specific stats within it. 64 */ 65struct ThreadState { 66 typedef ThreadContext::Status Status; 67 68#if FULL_SYSTEM 69 ThreadState(BaseCPU *cpu, int _cpuId, int _tid); 70#else 71 ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 72 short _asid); 73#endif 74 75 ~ThreadState(); 76 77 void serialize(std::ostream &os); 78 79 void unserialize(Checkpoint *cp, const std::string §ion); 80 81 void setCpuId(int id) { cpuId = id; } 82 83 int readCpuId() { return cpuId; } 84 85 void setTid(int id) { tid = id; } 86 87 int readTid() { return tid; } 88 89 Tick readLastActivate() { return lastActivate; } 90 91 Tick readLastSuspend() { return lastSuspend; } 92 93#if FULL_SYSTEM 94 void dumpFuncProfile(); 95 96 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 97 98 void profileClear(); 99 100 void profileSample(); 101 102 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 103 104 FunctionalPort *getPhysPort() { return physPort; } 105 106 void setPhysPort(FunctionalPort *port) { physPort = port; } 107 108 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; } 109 110 void setVirtPort(VirtualPort *port) { virtPort = port; } 111#else 112 Process *getProcessPtr() { return process; } 113 114 TranslatingPort *getMemPort(); 115 116 void setMemPort(TranslatingPort *_port) { port = _port; } 117 118 int getInstAsid() { return asid; } 119 int getDataAsid() { return asid; } 120#endif 121 122 /** Sets the current instruction being committed. */ 123 void setInst(TheISA::MachInst _inst) { inst = _inst; } 124 125 /** Returns the current instruction being committed. */ 126 TheISA::MachInst getInst() { return inst; } 127 128 /** Reads the number of instructions functionally executed and 129 * committed. 130 */ 131 Counter readFuncExeInst() { return funcExeInst; } 132 133 /** Sets the total number of instructions functionally executed 134 * and committed. 135 */ 136 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 137 138 /** Returns the status of this thread. */ 139 Status status() const { return _status; } 140 141 /** Sets the status of this thread. */ 142 void setStatus(Status new_status) { _status = new_status; } 143 144 public: 145 /** Gets a functional port from the memory object that's connected 146 * to the CPU. */ 147 Port *getMemFuncPort(); 148 149 /** Number of instructions committed. */ 150 Counter numInst; 151 /** Stat for number instructions committed. */ 152 Stats::Scalar<> numInsts; 153 /** Stat for number of memory references. */ 154 Stats::Scalar<> numMemRefs; 155 156 /** Number of simulated loads, used for tracking events based on 157 * the number of loads committed. 158 */ 159 Counter numLoad; 160 161 /** The number of simulated loads committed prior to this run. */ 162 Counter startNumLoad; 163 164 protected: 165 ThreadContext::Status _status; 166 167 // Pointer to the base CPU. 168 BaseCPU *baseCpu; 169 170 // ID of this context w.r.t. the System or Process object to which 171 // it belongs. For full-system mode, this is the system CPU ID. 172 int cpuId; 173 174 // Index of hardware thread context on the CPU that this represents. 175 int tid; 176 177 public: 178 /** Last time activate was called on this thread. */ 179 Tick lastActivate; 180 181 /** Last time suspend was called on this thread. */ 182 Tick lastSuspend; 183 184#if FULL_SYSTEM 185 public: 186 FunctionProfile *profile; 187 ProfileNode *profileNode; 188 Addr profilePC; 189 EndQuiesceEvent *quiesceEvent; 190 191 TheISA::Kernel::Statistics *kernelStats; 192 protected: 193 /** A functional port outgoing only for functional accesses to physical 194 * addresses.*/ 195 FunctionalPort *physPort; 196 197 /** A functional port, outgoing only, for functional accesse to virtual 198 * addresses. That doen't require execution context information */ 199 VirtualPort *virtPort; 200#else 201 TranslatingPort *port; 202 203 Process *process; 204 205 // Address space ID. Note that this is used for TIMING cache 206 // simulation only; all functional memory accesses should use 207 // one of the FunctionalMemory pointers above. 208 short asid; 209 210#endif 211 212 /** Current instruction the thread is committing. Only set and 213 * used for DTB faults currently. 214 */ 215 TheISA::MachInst inst; 216 217 /** The current microcode pc for the currently executing macro 218 * operation. 219 */ 220 MicroPC microPC; 221 222 /** The next microcode pc for the currently executing macro 223 * operation. 224 */ 225 MicroPC nextMicroPC; 226 227 public: 228 /** 229 * Temporary storage to pass the source address from copy_load to 230 * copy_store. 231 * @todo Remove this temporary when we have a better way to do it. 232 */ 233 Addr copySrcAddr; 234 /** 235 * Temp storage for the physical source address of a copy. 236 * @todo Remove this temporary when we have a better way to do it. 237 */ 238 Addr copySrcPhysAddr; 239 240 /* 241 * number of executed instructions, for matching with syscall trace 242 * points in EIO files. 243 */ 244 Counter funcExeInst; 245 246 // 247 // Count failed store conditionals so we can warn of apparent 248 // application deadlock situations. 249 unsigned storeCondFailures; 250}; 251 252#endif // __CPU_THREAD_STATE_HH__ 253