thread_state.hh revision 3402:db60546818d0 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_STATE_HH__
32#define __CPU_THREAD_STATE_HH__
33
34#include "arch/types.hh"
35#include "cpu/profile.hh"
36#include "cpu/thread_context.hh"
37
38#if !FULL_SYSTEM
39#include "mem/mem_object.hh"
40#include "sim/process.hh"
41#endif
42
43#if FULL_SYSTEM
44class EndQuiesceEvent;
45class FunctionProfile;
46class ProfileNode;
47namespace Kernel {
48    class Statistics;
49};
50#endif
51
52class BaseCPU;
53class Checkpoint;
54class TranslatingPort;
55
56/**
57 *  Struct for holding general thread state that is needed across CPU
58 *  models.  This includes things such as pointers to the process,
59 *  memory, quiesce events, and certain stats.  This can be expanded
60 *  to hold more thread-specific stats within it.
61 */
62struct ThreadState {
63    typedef ThreadContext::Status Status;
64
65#if FULL_SYSTEM
66    ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
67#else
68    ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
69                short _asid);
70#endif
71
72    void serialize(std::ostream &os);
73
74    void unserialize(Checkpoint *cp, const std::string &section);
75
76    void setCpuId(int id) { cpuId = id; }
77
78    int readCpuId() { return cpuId; }
79
80    void setTid(int id) { tid = id; }
81
82    int readTid() { return tid; }
83
84    Tick readLastActivate() { return lastActivate; }
85
86    Tick readLastSuspend() { return lastSuspend; }
87
88#if FULL_SYSTEM
89    void dumpFuncProfile();
90
91    EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
92
93    void profileClear();
94
95    void profileSample();
96
97    Kernel::Statistics *getKernelStats() { return kernelStats; }
98
99    FunctionalPort *getPhysPort() { return physPort; }
100
101    void setPhysPort(FunctionalPort *port) { physPort = port; }
102
103    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
104
105    void setVirtPort(VirtualPort *port) { virtPort = port; }
106#else
107    Process *getProcessPtr() { return process; }
108
109    TranslatingPort *getMemPort();
110
111    void setMemPort(TranslatingPort *_port) { port = _port; }
112
113    int getInstAsid() { return asid; }
114    int getDataAsid() { return asid; }
115#endif
116
117    /** Sets the current instruction being committed. */
118    void setInst(TheISA::MachInst _inst) { inst = _inst; }
119
120    /** Returns the current instruction being committed. */
121    TheISA::MachInst getInst() { return inst; }
122
123    /** Reads the number of instructions functionally executed and
124     * committed.
125     */
126    Counter readFuncExeInst() { return funcExeInst; }
127
128    /** Sets the total number of instructions functionally executed
129     * and committed.
130     */
131    void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
132
133    /** Returns the status of this thread. */
134    Status status() const { return _status; }
135
136    /** Sets the status of this thread. */
137    void setStatus(Status new_status) { _status = new_status; }
138
139    /** Number of instructions committed. */
140    Counter numInst;
141    /** Stat for number instructions committed. */
142    Stats::Scalar<> numInsts;
143    /** Stat for number of memory references. */
144    Stats::Scalar<> numMemRefs;
145
146    /** Number of simulated loads, used for tracking events based on
147     * the number of loads committed.
148     */
149    Counter numLoad;
150
151    /** The number of simulated loads committed prior to this run. */
152    Counter startNumLoad;
153
154  protected:
155    ThreadContext::Status _status;
156
157    // Pointer to the base CPU.
158    BaseCPU *baseCpu;
159
160    // ID of this context w.r.t. the System or Process object to which
161    // it belongs.  For full-system mode, this is the system CPU ID.
162    int cpuId;
163
164    // Index of hardware thread context on the CPU that this represents.
165    int tid;
166
167  public:
168    /** Last time activate was called on this thread. */
169    Tick lastActivate;
170
171    /** Last time suspend was called on this thread. */
172    Tick lastSuspend;
173
174#if FULL_SYSTEM
175  public:
176    FunctionProfile *profile;
177    ProfileNode *profileNode;
178    Addr profilePC;
179    EndQuiesceEvent *quiesceEvent;
180
181    Kernel::Statistics *kernelStats;
182  protected:
183    /** A functional port outgoing only for functional accesses to physical
184     * addresses.*/
185    FunctionalPort *physPort;
186
187    /** A functional port, outgoing only, for functional accesse to virtual
188     * addresses. That doen't require execution context information */
189    VirtualPort *virtPort;
190#else
191    TranslatingPort *port;
192
193    Process *process;
194
195    // Address space ID.  Note that this is used for TIMING cache
196    // simulation only; all functional memory accesses should use
197    // one of the FunctionalMemory pointers above.
198    short asid;
199
200#endif
201
202    /** Current instruction the thread is committing.  Only set and
203     * used for DTB faults currently.
204     */
205    TheISA::MachInst inst;
206
207    /** The current microcode pc for the currently executing macro
208     * operation.
209     */
210    MicroPC microPC;
211
212    /** The next microcode pc for the currently executing macro
213     * operation.
214     */
215    MicroPC nextMicroPC;
216
217  public:
218    /**
219     * Temporary storage to pass the source address from copy_load to
220     * copy_store.
221     * @todo Remove this temporary when we have a better way to do it.
222     */
223    Addr copySrcAddr;
224    /**
225     * Temp storage for the physical source address of a copy.
226     * @todo Remove this temporary when we have a better way to do it.
227     */
228    Addr copySrcPhysAddr;
229
230    /*
231     * number of executed instructions, for matching with syscall trace
232     * points in EIO files.
233     */
234    Counter funcExeInst;
235
236    //
237    // Count failed store conditionals so we can warn of apparent
238    // application deadlock situations.
239    unsigned storeCondFailures;
240};
241
242#endif // __CPU_THREAD_STATE_HH__
243