thread_state.hh revision 2733
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 311986Sandreas.sandberg@arm.com * All rights reserved. 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411986Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511986Sandreas.sandberg@arm.com * 1611986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911986Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111986Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311986Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411986Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511986Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611986Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711986Sandreas.sandberg@arm.com * 2811986Sandreas.sandberg@arm.com * Authors: Kevin Lim 2911986Sandreas.sandberg@arm.com */ 3011986Sandreas.sandberg@arm.com 3111986Sandreas.sandberg@arm.com#ifndef __CPU_THREAD_STATE_HH__ 3211986Sandreas.sandberg@arm.com#define __CPU_THREAD_STATE_HH__ 3311986Sandreas.sandberg@arm.com 3411986Sandreas.sandberg@arm.com#include "arch/isa_traits.hh" 3511986Sandreas.sandberg@arm.com#include "cpu/thread_context.hh" 3611986Sandreas.sandberg@arm.com 3711986Sandreas.sandberg@arm.com#if !FULL_SYSTEM 3811986Sandreas.sandberg@arm.com#include "mem/mem_object.hh" 3911986Sandreas.sandberg@arm.com#include "mem/translating_port.hh" 4011986Sandreas.sandberg@arm.com#include "sim/process.hh" 4111986Sandreas.sandberg@arm.com#endif 4211986Sandreas.sandberg@arm.com 4311986Sandreas.sandberg@arm.com#if FULL_SYSTEM 4411986Sandreas.sandberg@arm.comclass EndQuiesceEvent; 4511986Sandreas.sandberg@arm.comclass FunctionProfile; 4611986Sandreas.sandberg@arm.comclass ProfileNode; 4711986Sandreas.sandberg@arm.comnamespace Kernel { 4811986Sandreas.sandberg@arm.com class Statistics; 4911986Sandreas.sandberg@arm.com}; 5011986Sandreas.sandberg@arm.com#endif 5111986Sandreas.sandberg@arm.com 5211986Sandreas.sandberg@arm.com/** 5311986Sandreas.sandberg@arm.com * Struct for holding general thread state that is needed across CPU 5411986Sandreas.sandberg@arm.com * models. This includes things such as pointers to the process, 5511986Sandreas.sandberg@arm.com * memory, quiesce events, and certain stats. This can be expanded 5611986Sandreas.sandberg@arm.com * to hold more thread-specific stats within it. 5711986Sandreas.sandberg@arm.com */ 5811986Sandreas.sandberg@arm.comstruct ThreadState { 5911986Sandreas.sandberg@arm.com typedef ThreadContext::Status Status; 6011986Sandreas.sandberg@arm.com 6111986Sandreas.sandberg@arm.com#if FULL_SYSTEM 6211986Sandreas.sandberg@arm.com ThreadState(int _cpuId, int _tid); 6311986Sandreas.sandberg@arm.com#else 6411986Sandreas.sandberg@arm.com ThreadState(int _cpuId, int _tid, MemObject *mem, 6511986Sandreas.sandberg@arm.com Process *_process, short _asid); 6611986Sandreas.sandberg@arm.com#endif 67 68 void setCpuId(int id) { cpuId = id; } 69 70 int readCpuId() { return cpuId; } 71 72 void setTid(int id) { tid = id; } 73 74 int readTid() { return tid; } 75 76 Tick readLastActivate() { return lastActivate; } 77 78 Tick readLastSuspend() { return lastSuspend; } 79 80#if FULL_SYSTEM 81 void dumpFuncProfile(); 82 83 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 84 85 void profileClear(); 86 87 void profileSample(); 88 89 Kernel::Statistics *getKernelStats() { return kernelStats; } 90 91 FunctionalPort *getPhysPort() { return physPort; } 92 93 void setPhysPort(FunctionalPort *port) { physPort = port; } 94 95 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; } 96 97 void setVirtPort(VirtualPort *port) { virtPort = port; } 98#else 99 Process *getProcessPtr() { return process; } 100 101 TranslatingPort *getMemPort() { return port; } 102 103 void setMemPort(TranslatingPort *_port) { port = _port; } 104 105 int getInstAsid() { return asid; } 106 int getDataAsid() { return asid; } 107#endif 108 109 /** Sets the current instruction being committed. */ 110 void setInst(TheISA::MachInst _inst) { inst = _inst; } 111 112 /** Returns the current instruction being committed. */ 113 TheISA::MachInst getInst() { return inst; } 114 115 /** Reads the number of instructions functionally executed and 116 * committed. 117 */ 118 Counter readFuncExeInst() { return funcExeInst; } 119 120 /** Sets the total number of instructions functionally executed 121 * and committed. 122 */ 123 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 124 125 /** Returns the status of this thread. */ 126 Status status() const { return _status; } 127 128 /** Sets the status of this thread. */ 129 void setStatus(Status new_status) { _status = new_status; } 130 131 /** Number of instructions committed. */ 132 Counter numInst; 133 /** Stat for number instructions committed. */ 134 Stats::Scalar<> numInsts; 135 /** Stat for number of memory references. */ 136 Stats::Scalar<> numMemRefs; 137 138 /** Number of simulated loads, used for tracking events based on 139 * the number of loads committed. 140 */ 141 Counter numLoad; 142 143 /** The number of simulated loads committed prior to this run. */ 144 Counter startNumLoad; 145 146 protected: 147 ThreadContext::Status _status; 148 149 // ID of this context w.r.t. the System or Process object to which 150 // it belongs. For full-system mode, this is the system CPU ID. 151 int cpuId; 152 153 // Index of hardware thread context on the CPU that this represents. 154 int tid; 155 156 public: 157 /** Last time activate was called on this thread. */ 158 Tick lastActivate; 159 160 /** Last time suspend was called on this thread. */ 161 Tick lastSuspend; 162 163#if FULL_SYSTEM 164 public: 165 FunctionProfile *profile; 166 ProfileNode *profileNode; 167 Addr profilePC; 168 EndQuiesceEvent *quiesceEvent; 169 170 Kernel::Statistics *kernelStats; 171 protected: 172 /** A functional port outgoing only for functional accesses to physical 173 * addresses.*/ 174 FunctionalPort *physPort; 175 176 /** A functional port, outgoing only, for functional accesse to virtual 177 * addresses. That doen't require execution context information */ 178 VirtualPort *virtPort; 179#else 180 TranslatingPort *port; 181 182 Process *process; 183 184 // Address space ID. Note that this is used for TIMING cache 185 // simulation only; all functional memory accesses should use 186 // one of the FunctionalMemory pointers above. 187 short asid; 188#endif 189 190 /** Current instruction the thread is committing. Only set and 191 * used for DTB faults currently. 192 */ 193 TheISA::MachInst inst; 194 195 public: 196 /** 197 * Temporary storage to pass the source address from copy_load to 198 * copy_store. 199 * @todo Remove this temporary when we have a better way to do it. 200 */ 201 Addr copySrcAddr; 202 /** 203 * Temp storage for the physical source address of a copy. 204 * @todo Remove this temporary when we have a better way to do it. 205 */ 206 Addr copySrcPhysAddr; 207 208 /* 209 * number of executed instructions, for matching with syscall trace 210 * points in EIO files. 211 */ 212 Counter funcExeInst; 213 214 // 215 // Count failed store conditionals so we can warn of apparent 216 // application deadlock situations. 217 unsigned storeCondFailures; 218}; 219 220#endif // __CPU_THREAD_STATE_HH__ 221