thread_state.hh revision 13905:5cf30883255c
17404SAli.Saidi@ARM.com/* 210717Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 37404SAli.Saidi@ARM.com * All rights reserved. 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147404SAli.Saidi@ARM.com * this software without specific prior written permission. 157404SAli.Saidi@ARM.com * 167404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277404SAli.Saidi@ARM.com * 287404SAli.Saidi@ARM.com * Authors: Kevin Lim 297404SAli.Saidi@ARM.com */ 307404SAli.Saidi@ARM.com 317404SAli.Saidi@ARM.com#ifndef __CPU_THREAD_STATE_HH__ 327404SAli.Saidi@ARM.com#define __CPU_THREAD_STATE_HH__ 337404SAli.Saidi@ARM.com 347404SAli.Saidi@ARM.com#include "arch/types.hh" 357404SAli.Saidi@ARM.com#include "config/the_isa.hh" 367404SAli.Saidi@ARM.com#include "cpu/base.hh" 377404SAli.Saidi@ARM.com#include "cpu/profile.hh" 3810037SARM gem5 Developers#include "cpu/thread_context.hh" 397404SAli.Saidi@ARM.com#include "sim/process.hh" 407404SAli.Saidi@ARM.com 417404SAli.Saidi@ARM.comclass EndQuiesceEvent; 427404SAli.Saidi@ARM.comclass FunctionProfile; 437404SAli.Saidi@ARM.comclass ProfileNode; 447578Sdam.sunwoo@arm.comnamespace Kernel { 457578Sdam.sunwoo@arm.com class Statistics; 467404SAli.Saidi@ARM.com} 4710037SARM gem5 Developers 487404SAli.Saidi@ARM.comclass Checkpoint; 497404SAli.Saidi@ARM.com 507404SAli.Saidi@ARM.com/** 517404SAli.Saidi@ARM.com * Struct for holding general thread state that is needed across CPU 527404SAli.Saidi@ARM.com * models. This includes things such as pointers to the process, 537404SAli.Saidi@ARM.com * memory, quiesce events, and certain stats. This can be expanded 547404SAli.Saidi@ARM.com * to hold more thread-specific stats within it. 5510873Sandreas.sandberg@arm.com */ 5610873Sandreas.sandberg@arm.comstruct ThreadState : public Serializable { 577404SAli.Saidi@ARM.com typedef ThreadContext::Status Status; 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.com ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process); 6010037SARM gem5 Developers 617404SAli.Saidi@ARM.com virtual ~ThreadState(); 627404SAli.Saidi@ARM.com 637404SAli.Saidi@ARM.com void serialize(CheckpointOut &cp) const override; 647694SAli.Saidi@ARM.com 6510037SARM gem5 Developers void unserialize(CheckpointIn &cp) override; 6610037SARM gem5 Developers 6710037SARM gem5 Developers int cpuId() const { return baseCpu->cpuId(); } 6810037SARM gem5 Developers 6910037SARM gem5 Developers uint32_t socketId() const { return baseCpu->socketId(); } 7010037SARM gem5 Developers 7110037SARM gem5 Developers ContextID contextId() const { return _contextId; } 7210037SARM gem5 Developers 7310037SARM gem5 Developers void setContextId(ContextID id) { _contextId = id; } 7410037SARM gem5 Developers 7510037SARM gem5 Developers void setThreadId(ThreadID id) { _threadId = id; } 7610037SARM gem5 Developers 7710037SARM gem5 Developers ThreadID threadId() const { return _threadId; } 7810037SARM gem5 Developers 7910037SARM gem5 Developers Tick readLastActivate() const { return lastActivate; } 8010037SARM gem5 Developers 8110037SARM gem5 Developers Tick readLastSuspend() const { return lastSuspend; } 8210037SARM gem5 Developers 8310037SARM gem5 Developers /** 8410037SARM gem5 Developers * Initialise the physical and virtual port proxies and tie them to 8510037SARM gem5 Developers * the data port of the CPU. 8610037SARM gem5 Developers * 8710037SARM gem5 Developers * @param tc ThreadContext for the virtual-to-physical translation 8810037SARM gem5 Developers */ 8910037SARM gem5 Developers void initMemProxies(ThreadContext *tc); 9010037SARM gem5 Developers 9110037SARM gem5 Developers void dumpFuncProfile(); 9210037SARM gem5 Developers 937404SAli.Saidi@ARM.com EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 947404SAli.Saidi@ARM.com 957404SAli.Saidi@ARM.com void profileClear(); 967404SAli.Saidi@ARM.com 977404SAli.Saidi@ARM.com void profileSample(); 987404SAli.Saidi@ARM.com 997404SAli.Saidi@ARM.com Kernel::Statistics *getKernelStats() { return kernelStats; } 1007404SAli.Saidi@ARM.com 1017436Sdam.sunwoo@arm.com PortProxy &getPhysProxy(); 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.com FSTranslatingPortProxy &getVirtProxy(); 1047436Sdam.sunwoo@arm.com 1057436Sdam.sunwoo@arm.com Process *getProcessPtr() { return process; } 1067436Sdam.sunwoo@arm.com 1077436Sdam.sunwoo@arm.com void setProcessPtr(Process *p) 10810037SARM gem5 Developers { 10910537Sandreas.hansson@arm.com process = p; 11010037SARM gem5 Developers /** 11110037SARM gem5 Developers * When the process pointer changes while operating in SE Mode, 11210037SARM gem5 Developers * the se translating port proxy needs to be reinitialized since it 11310037SARM gem5 Developers * holds a pointer to the process class. 11410037SARM gem5 Developers */ 11510037SARM gem5 Developers if (proxy) { 11610037SARM gem5 Developers delete proxy; 11710037SARM gem5 Developers proxy = NULL; 11810037SARM gem5 Developers initMemProxies(NULL); 11910037SARM gem5 Developers } 12010037SARM gem5 Developers } 12110037SARM gem5 Developers 12210037SARM gem5 Developers SETranslatingPortProxy &getMemProxy(); 12310037SARM gem5 Developers 12410037SARM gem5 Developers /** Reads the number of instructions functionally executed and 12510037SARM gem5 Developers * committed. 12610037SARM gem5 Developers */ 12710037SARM gem5 Developers Counter readFuncExeInst() const { return funcExeInst; } 12810037SARM gem5 Developers 1297404SAli.Saidi@ARM.com /** Sets the total number of instructions functionally executed 1307404SAli.Saidi@ARM.com * and committed. 1317404SAli.Saidi@ARM.com */ 1327404SAli.Saidi@ARM.com void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 1337404SAli.Saidi@ARM.com 1347404SAli.Saidi@ARM.com /** Returns the status of this thread. */ 1357404SAli.Saidi@ARM.com Status status() const { return _status; } 1367404SAli.Saidi@ARM.com 1377404SAli.Saidi@ARM.com /** Sets the status of this thread. */ 1387404SAli.Saidi@ARM.com void setStatus(Status new_status) { _status = new_status; } 1397404SAli.Saidi@ARM.com 1407404SAli.Saidi@ARM.com public: 1417404SAli.Saidi@ARM.com 1427404SAli.Saidi@ARM.com /** Number of instructions committed. */ 1437404SAli.Saidi@ARM.com Counter numInst; 1447404SAli.Saidi@ARM.com /** Stat for number instructions committed. */ 1457946SGiacomo.Gabrielli@arm.com Stats::Scalar numInsts; 1467404SAli.Saidi@ARM.com /** Number of ops (including micro ops) committed. */ 1477694SAli.Saidi@ARM.com Counter numOp; 1487694SAli.Saidi@ARM.com /** Stat for number ops (including micro ops) committed. */ 1497694SAli.Saidi@ARM.com Stats::Scalar numOps; 1507694SAli.Saidi@ARM.com /** Stat for number of memory references. */ 1517694SAli.Saidi@ARM.com Stats::Scalar numMemRefs; 1527946SGiacomo.Gabrielli@arm.com 1537694SAli.Saidi@ARM.com /** Number of simulated loads, used for tracking events based on 1547694SAli.Saidi@ARM.com * the number of loads committed. 1557404SAli.Saidi@ARM.com */ 1567404SAli.Saidi@ARM.com Counter numLoad; 1577404SAli.Saidi@ARM.com 1587404SAli.Saidi@ARM.com /** The number of simulated loads committed prior to this run. */ 1597404SAli.Saidi@ARM.com Counter startNumLoad; 1607404SAli.Saidi@ARM.com 1617946SGiacomo.Gabrielli@arm.com protected: 1627404SAli.Saidi@ARM.com ThreadContext::Status _status; 1637404SAli.Saidi@ARM.com 1647404SAli.Saidi@ARM.com // Pointer to the base CPU. 16510037SARM gem5 Developers BaseCPU *baseCpu; 1667404SAli.Saidi@ARM.com 16710037SARM gem5 Developers // system wide HW context id 1687404SAli.Saidi@ARM.com ContextID _contextId; 1697404SAli.Saidi@ARM.com 1707404SAli.Saidi@ARM.com // Index of hardware thread context on the CPU that this represents. 1717404SAli.Saidi@ARM.com ThreadID _threadId; 1727404SAli.Saidi@ARM.com 1737608SGene.Wu@arm.com public: 1747404SAli.Saidi@ARM.com /** Last time activate was called on this thread. */ 1757404SAli.Saidi@ARM.com Tick lastActivate; 1767404SAli.Saidi@ARM.com 1777404SAli.Saidi@ARM.com /** Last time suspend was called on this thread. */ 1787404SAli.Saidi@ARM.com Tick lastSuspend; 1797946SGiacomo.Gabrielli@arm.com 1807404SAli.Saidi@ARM.com public: 1817404SAli.Saidi@ARM.com FunctionProfile *profile; 1827404SAli.Saidi@ARM.com ProfileNode *profileNode; 18310037SARM gem5 Developers Addr profilePC; 1847404SAli.Saidi@ARM.com EndQuiesceEvent *quiesceEvent; 18510037SARM gem5 Developers 1867404SAli.Saidi@ARM.com Kernel::Statistics *kernelStats; 1877404SAli.Saidi@ARM.com 1887404SAli.Saidi@ARM.com protected: 1897404SAli.Saidi@ARM.com Process *process; 1907404SAli.Saidi@ARM.com 1917946SGiacomo.Gabrielli@arm.com /** A port proxy outgoing only for functional accesses to physical 1927404SAli.Saidi@ARM.com * addresses.*/ 1937404SAli.Saidi@ARM.com PortProxy *physProxy; 1947436Sdam.sunwoo@arm.com 1957436Sdam.sunwoo@arm.com /** A translating port proxy, outgoing only, for functional 1967436Sdam.sunwoo@arm.com * accesse to virtual addresses. */ 1977436Sdam.sunwoo@arm.com FSTranslatingPortProxy *virtProxy; 1987436Sdam.sunwoo@arm.com SETranslatingPortProxy *proxy; 1997404SAli.Saidi@ARM.com 2007404SAli.Saidi@ARM.com public: 2017946SGiacomo.Gabrielli@arm.com /* 2027404SAli.Saidi@ARM.com * number of executed instructions, for matching with syscall trace 2037404SAli.Saidi@ARM.com * points in EIO files. 2047436Sdam.sunwoo@arm.com */ 2057436Sdam.sunwoo@arm.com Counter funcExeInst; 2067436Sdam.sunwoo@arm.com 2077436Sdam.sunwoo@arm.com // 2087436Sdam.sunwoo@arm.com // Count failed store conditionals so we can warn of apparent 2097436Sdam.sunwoo@arm.com // application deadlock situations. 2107436Sdam.sunwoo@arm.com unsigned storeCondFailures; 2117436Sdam.sunwoo@arm.com}; 2127436Sdam.sunwoo@arm.com 2137436Sdam.sunwoo@arm.com#endif // __CPU_THREAD_STATE_HH__ 2147436Sdam.sunwoo@arm.com