thread_state.hh revision 8229
12735Sktlim@umich.edu/*
210319SAndreas.Sandberg@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan
310319SAndreas.Sandberg@ARM.com * All rights reserved.
410319SAndreas.Sandberg@ARM.com *
510319SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without
610319SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are
710319SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright
810319SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer;
910319SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright
1010319SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the
1110319SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution;
1210319SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its
1310319SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from
142735Sktlim@umich.edu * this software without specific prior written permission.
1511303Ssteve.reinhardt@amd.com *
162735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272735Sktlim@umich.edu *
282735Sktlim@umich.edu * Authors: Kevin Lim
292735Sktlim@umich.edu */
302735Sktlim@umich.edu
312735Sktlim@umich.edu#ifndef __CPU_THREAD_STATE_HH__
322735Sktlim@umich.edu#define __CPU_THREAD_STATE_HH__
332735Sktlim@umich.edu
342735Sktlim@umich.edu#include "arch/types.hh"
352735Sktlim@umich.edu#include "config/the_isa.hh"
362735Sktlim@umich.edu#include "cpu/base.hh"
372735Sktlim@umich.edu#include "cpu/profile.hh"
382735Sktlim@umich.edu#include "cpu/thread_context.hh"
392735Sktlim@umich.edu
402735Sktlim@umich.edu#if !FULL_SYSTEM
412735Sktlim@umich.edu#include "mem/mem_object.hh"
4210319SAndreas.Sandberg@ARM.com#include "sim/process.hh"
432735Sktlim@umich.edu#endif
442735Sktlim@umich.edu
4510319SAndreas.Sandberg@ARM.com#if FULL_SYSTEM
4610319SAndreas.Sandberg@ARM.comclass EndQuiesceEvent;
4710319SAndreas.Sandberg@ARM.comclass FunctionProfile;
4810319SAndreas.Sandberg@ARM.comclass ProfileNode;
4910319SAndreas.Sandberg@ARM.comnamespace TheISA {
5010319SAndreas.Sandberg@ARM.com    namespace Kernel {
5110529Smorr@cs.wisc.edu        class Statistics;
5210319SAndreas.Sandberg@ARM.com    };
5310319SAndreas.Sandberg@ARM.com};
5411608Snikos.nikoleris@arm.com#endif
552735Sktlim@umich.edu
562735Sktlim@umich.educlass Checkpoint;
5710319SAndreas.Sandberg@ARM.comclass Port;
5810319SAndreas.Sandberg@ARM.comclass TranslatingPort;
5910319SAndreas.Sandberg@ARM.com
6010319SAndreas.Sandberg@ARM.com/**
6110319SAndreas.Sandberg@ARM.com *  Struct for holding general thread state that is needed across CPU
6210319SAndreas.Sandberg@ARM.com *  models.  This includes things such as pointers to the process,
6310319SAndreas.Sandberg@ARM.com *  memory, quiesce events, and certain stats.  This can be expanded
6410319SAndreas.Sandberg@ARM.com *  to hold more thread-specific stats within it.
6510319SAndreas.Sandberg@ARM.com */
6610319SAndreas.Sandberg@ARM.comstruct ThreadState {
6710319SAndreas.Sandberg@ARM.com    typedef ThreadContext::Status Status;
6810319SAndreas.Sandberg@ARM.com
6910319SAndreas.Sandberg@ARM.com#if FULL_SYSTEM
7010319SAndreas.Sandberg@ARM.com    ThreadState(BaseCPU *cpu, ThreadID _tid);
712735Sktlim@umich.edu#else
722735Sktlim@umich.edu    ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
7310319SAndreas.Sandberg@ARM.com#endif
7410319SAndreas.Sandberg@ARM.com
7510319SAndreas.Sandberg@ARM.com    ~ThreadState();
7610319SAndreas.Sandberg@ARM.com
7710319SAndreas.Sandberg@ARM.com    void serialize(std::ostream &os);
7810319SAndreas.Sandberg@ARM.com
7910319SAndreas.Sandberg@ARM.com    void unserialize(Checkpoint *cp, const std::string &section);
8010319SAndreas.Sandberg@ARM.com
8110319SAndreas.Sandberg@ARM.com    int cpuId() { return baseCpu->cpuId(); }
8210319SAndreas.Sandberg@ARM.com
8310319SAndreas.Sandberg@ARM.com    int contextId() { return _contextId; }
8410319SAndreas.Sandberg@ARM.com
8510319SAndreas.Sandberg@ARM.com    void setContextId(int id) { _contextId = id; }
8610319SAndreas.Sandberg@ARM.com
8710319SAndreas.Sandberg@ARM.com    void setThreadId(ThreadID id) { _threadId = id; }
882735Sktlim@umich.edu
892735Sktlim@umich.edu    ThreadID threadId() { return _threadId; }
9010319SAndreas.Sandberg@ARM.com
9110319SAndreas.Sandberg@ARM.com    Tick readLastActivate() { return lastActivate; }
9210319SAndreas.Sandberg@ARM.com
9310319SAndreas.Sandberg@ARM.com    Tick readLastSuspend() { return lastSuspend; }
9410319SAndreas.Sandberg@ARM.com
9510319SAndreas.Sandberg@ARM.com#if FULL_SYSTEM
9610319SAndreas.Sandberg@ARM.com    void connectMemPorts(ThreadContext *tc);
9710319SAndreas.Sandberg@ARM.com
9810319SAndreas.Sandberg@ARM.com    void connectPhysPort();
9910319SAndreas.Sandberg@ARM.com
10010319SAndreas.Sandberg@ARM.com    void connectVirtPort(ThreadContext *tc);
10110319SAndreas.Sandberg@ARM.com
10210319SAndreas.Sandberg@ARM.com    void dumpFuncProfile();
1032735Sktlim@umich.edu
1042735Sktlim@umich.edu    EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
10510319SAndreas.Sandberg@ARM.com
1062735Sktlim@umich.edu    void profileClear();
1072735Sktlim@umich.edu
1082735Sktlim@umich.edu    void profileSample();
10910319SAndreas.Sandberg@ARM.com
11010319SAndreas.Sandberg@ARM.com    TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
1112735Sktlim@umich.edu
1122735Sktlim@umich.edu    FunctionalPort *getPhysPort() { return physPort; }
11310319SAndreas.Sandberg@ARM.com
11410319SAndreas.Sandberg@ARM.com    void setPhysPort(FunctionalPort *port) { physPort = port; }
1152735Sktlim@umich.edu
1162735Sktlim@umich.edu    VirtualPort *getVirtPort() { return virtPort; }
1172735Sktlim@umich.edu#else
11810319SAndreas.Sandberg@ARM.com    Process *getProcessPtr() { return process; }
11910319SAndreas.Sandberg@ARM.com
1202735Sktlim@umich.edu    TranslatingPort *getMemPort();
12110319SAndreas.Sandberg@ARM.com
1222735Sktlim@umich.edu    void setMemPort(TranslatingPort *_port) { port = _port; }
12310319SAndreas.Sandberg@ARM.com#endif
12410319SAndreas.Sandberg@ARM.com
12510319SAndreas.Sandberg@ARM.com    /** Reads the number of instructions functionally executed and
12610319SAndreas.Sandberg@ARM.com     * committed.
12710319SAndreas.Sandberg@ARM.com     */
12810319SAndreas.Sandberg@ARM.com    Counter readFuncExeInst() { return funcExeInst; }
12910319SAndreas.Sandberg@ARM.com
1302735Sktlim@umich.edu    /** Sets the total number of instructions functionally executed
13110319SAndreas.Sandberg@ARM.com     * and committed.
13210319SAndreas.Sandberg@ARM.com     */
13310319SAndreas.Sandberg@ARM.com    void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
13410319SAndreas.Sandberg@ARM.com
13510319SAndreas.Sandberg@ARM.com    /** Returns the status of this thread. */
13610319SAndreas.Sandberg@ARM.com    Status status() const { return _status; }
13710319SAndreas.Sandberg@ARM.com
1382735Sktlim@umich.edu    /** Sets the status of this thread. */
13910319SAndreas.Sandberg@ARM.com    void setStatus(Status new_status) { _status = new_status; }
14010319SAndreas.Sandberg@ARM.com
14110319SAndreas.Sandberg@ARM.com  public:
14210319SAndreas.Sandberg@ARM.com    /** Connects port to the functional port of the memory object
14310319SAndreas.Sandberg@ARM.com     * below the CPU. */
1442735Sktlim@umich.edu    void connectToMemFunc(Port *port);
14510319SAndreas.Sandberg@ARM.com
14610319SAndreas.Sandberg@ARM.com    /** Number of instructions committed. */
14710319SAndreas.Sandberg@ARM.com    Counter numInst;
14810319SAndreas.Sandberg@ARM.com    /** Stat for number instructions committed. */
14910319SAndreas.Sandberg@ARM.com    Stats::Scalar numInsts;
1502735Sktlim@umich.edu    /** Stat for number of memory references. */
15110319SAndreas.Sandberg@ARM.com    Stats::Scalar numMemRefs;
1522735Sktlim@umich.edu
15310319SAndreas.Sandberg@ARM.com    /** Number of simulated loads, used for tracking events based on
15410319SAndreas.Sandberg@ARM.com     * the number of loads committed.
15510319SAndreas.Sandberg@ARM.com     */
15610319SAndreas.Sandberg@ARM.com    Counter numLoad;
15710319SAndreas.Sandberg@ARM.com
15810319SAndreas.Sandberg@ARM.com    /** The number of simulated loads committed prior to this run. */
15910319SAndreas.Sandberg@ARM.com    Counter startNumLoad;
16010319SAndreas.Sandberg@ARM.com
16110319SAndreas.Sandberg@ARM.com  protected:
16210319SAndreas.Sandberg@ARM.com    ThreadContext::Status _status;
16310319SAndreas.Sandberg@ARM.com
16410319SAndreas.Sandberg@ARM.com    // Pointer to the base CPU.
16510319SAndreas.Sandberg@ARM.com    BaseCPU *baseCpu;
16610319SAndreas.Sandberg@ARM.com
16710319SAndreas.Sandberg@ARM.com    // system wide HW context id
16810319SAndreas.Sandberg@ARM.com    int _contextId;
16910319SAndreas.Sandberg@ARM.com
17010319SAndreas.Sandberg@ARM.com    // Index of hardware thread context on the CPU that this represents.
17110319SAndreas.Sandberg@ARM.com    ThreadID _threadId;
17210319SAndreas.Sandberg@ARM.com
17310319SAndreas.Sandberg@ARM.com  public:
17410319SAndreas.Sandberg@ARM.com    /** Last time activate was called on this thread. */
17510319SAndreas.Sandberg@ARM.com    Tick lastActivate;
17610319SAndreas.Sandberg@ARM.com
17710319SAndreas.Sandberg@ARM.com    /** Last time suspend was called on this thread. */
17811303Ssteve.reinhardt@amd.com    Tick lastSuspend;
17911303Ssteve.reinhardt@amd.com
18011303Ssteve.reinhardt@amd.com#if FULL_SYSTEM
18111303Ssteve.reinhardt@amd.com  public:
18211303Ssteve.reinhardt@amd.com    FunctionProfile *profile;
18311303Ssteve.reinhardt@amd.com    ProfileNode *profileNode;
18411303Ssteve.reinhardt@amd.com    Addr profilePC;
18510319SAndreas.Sandberg@ARM.com    EndQuiesceEvent *quiesceEvent;
18611608Snikos.nikoleris@arm.com
18711303Ssteve.reinhardt@amd.com    TheISA::Kernel::Statistics *kernelStats;
18811303Ssteve.reinhardt@amd.com  protected:
18911303Ssteve.reinhardt@amd.com    /** A functional port outgoing only for functional accesses to physical
19010319SAndreas.Sandberg@ARM.com     * addresses.*/
19111303Ssteve.reinhardt@amd.com    FunctionalPort *physPort;
19211303Ssteve.reinhardt@amd.com
19311303Ssteve.reinhardt@amd.com    /** A functional port, outgoing only, for functional accesse to virtual
19411303Ssteve.reinhardt@amd.com     * addresses. */
19511303Ssteve.reinhardt@amd.com    VirtualPort *virtPort;
19611303Ssteve.reinhardt@amd.com#else
19711303Ssteve.reinhardt@amd.com    TranslatingPort *port;
19811303Ssteve.reinhardt@amd.com
19911608Snikos.nikoleris@arm.com    Process *process;
20011303Ssteve.reinhardt@amd.com#endif
20111303Ssteve.reinhardt@amd.com
20211303Ssteve.reinhardt@amd.com  public:
20311303Ssteve.reinhardt@amd.com    /*
20411303Ssteve.reinhardt@amd.com     * number of executed instructions, for matching with syscall trace
20511303Ssteve.reinhardt@amd.com     * points in EIO files.
20611303Ssteve.reinhardt@amd.com     */
20711303Ssteve.reinhardt@amd.com    Counter funcExeInst;
20810319SAndreas.Sandberg@ARM.com
20911608Snikos.nikoleris@arm.com    //
21010319SAndreas.Sandberg@ARM.com    // Count failed store conditionals so we can warn of apparent
21110319SAndreas.Sandberg@ARM.com    // application deadlock situations.
21210319SAndreas.Sandberg@ARM.com    unsigned storeCondFailures;
21310319SAndreas.Sandberg@ARM.com};
21410319SAndreas.Sandberg@ARM.com
21510319SAndreas.Sandberg@ARM.com#endif // __CPU_THREAD_STATE_HH__
21610319SAndreas.Sandberg@ARM.com