thread_state.hh revision 5715
12330SN/A/* 22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292330SN/A */ 302292SN/A 312292SN/A#ifndef __CPU_THREAD_STATE_HH__ 322292SN/A#define __CPU_THREAD_STATE_HH__ 332292SN/A 342980Sgblack@eecs.umich.edu#include "arch/types.hh" 352362SN/A#include "cpu/profile.hh" 362680Sktlim@umich.edu#include "cpu/thread_context.hh" 375712Shsul@eecs.umich.edu#include "cpu/base.hh" 382292SN/A 392678Sktlim@umich.edu#if !FULL_SYSTEM 402683Sktlim@umich.edu#include "mem/mem_object.hh" 412683Sktlim@umich.edu#include "sim/process.hh" 422678Sktlim@umich.edu#endif 432678Sktlim@umich.edu 442292SN/A#if FULL_SYSTEM 452292SN/Aclass EndQuiesceEvent; 462292SN/Aclass FunctionProfile; 472292SN/Aclass ProfileNode; 483548Sgblack@eecs.umich.edunamespace TheISA { 493548Sgblack@eecs.umich.edu namespace Kernel { 503548Sgblack@eecs.umich.edu class Statistics; 513548Sgblack@eecs.umich.edu }; 522330SN/A}; 532292SN/A#endif 542292SN/A 552862Sktlim@umich.educlass Checkpoint; 563486Sktlim@umich.educlass Port; 573402Sktlim@umich.educlass TranslatingPort; 582862Sktlim@umich.edu 592330SN/A/** 602330SN/A * Struct for holding general thread state that is needed across CPU 612330SN/A * models. This includes things such as pointers to the process, 622330SN/A * memory, quiesce events, and certain stats. This can be expanded 632330SN/A * to hold more thread-specific stats within it. 642330SN/A */ 652292SN/Astruct ThreadState { 662683Sktlim@umich.edu typedef ThreadContext::Status Status; 672683Sktlim@umich.edu 682292SN/A#if FULL_SYSTEM 695712Shsul@eecs.umich.edu ThreadState(BaseCPU *cpu, int _tid); 702292SN/A#else 715712Shsul@eecs.umich.edu ThreadState(BaseCPU *cpu, int _tid, Process *_process, 723402Sktlim@umich.edu short _asid); 732292SN/A#endif 742683Sktlim@umich.edu 753486Sktlim@umich.edu ~ThreadState(); 763486Sktlim@umich.edu 772862Sktlim@umich.edu void serialize(std::ostream &os); 782862Sktlim@umich.edu 792862Sktlim@umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 802862Sktlim@umich.edu 815712Shsul@eecs.umich.edu int cpuId() { return baseCpu->cpuId(); } 822683Sktlim@umich.edu 835714Shsul@eecs.umich.edu int contextId() { return _contextId; } 845714Shsul@eecs.umich.edu 855714Shsul@eecs.umich.edu void setContextId(int id) { _contextId = id; } 865714Shsul@eecs.umich.edu 875715Shsul@eecs.umich.edu void setThreadId(int id) { _threadId = id; } 882683Sktlim@umich.edu 895715Shsul@eecs.umich.edu int threadId() { return _threadId; } 902683Sktlim@umich.edu 912683Sktlim@umich.edu Tick readLastActivate() { return lastActivate; } 922683Sktlim@umich.edu 932683Sktlim@umich.edu Tick readLastSuspend() { return lastSuspend; } 942683Sktlim@umich.edu 952683Sktlim@umich.edu#if FULL_SYSTEM 965497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc); 973675Sktlim@umich.edu 983686Sktlim@umich.edu void connectPhysPort(); 993675Sktlim@umich.edu 1005497Ssaidi@eecs.umich.edu void connectVirtPort(ThreadContext *tc); 1013675Sktlim@umich.edu 1022683Sktlim@umich.edu void dumpFuncProfile(); 1032683Sktlim@umich.edu 1042683Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 1052683Sktlim@umich.edu 1062683Sktlim@umich.edu void profileClear(); 1072683Sktlim@umich.edu 1082683Sktlim@umich.edu void profileSample(); 1092683Sktlim@umich.edu 1103548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 1112683Sktlim@umich.edu 1122690Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 1132690Sktlim@umich.edu 1142683Sktlim@umich.edu void setPhysPort(FunctionalPort *port) { physPort = port; } 1152683Sktlim@umich.edu 1165499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 1172683Sktlim@umich.edu#else 1182683Sktlim@umich.edu Process *getProcessPtr() { return process; } 1192683Sktlim@umich.edu 1203402Sktlim@umich.edu TranslatingPort *getMemPort(); 1212683Sktlim@umich.edu 1222683Sktlim@umich.edu void setMemPort(TranslatingPort *_port) { port = _port; } 1232683Sktlim@umich.edu 1242683Sktlim@umich.edu int getInstAsid() { return asid; } 1252683Sktlim@umich.edu int getDataAsid() { return asid; } 1262678Sktlim@umich.edu#endif 1272292SN/A 1282683Sktlim@umich.edu /** Sets the current instruction being committed. */ 1292683Sktlim@umich.edu void setInst(TheISA::MachInst _inst) { inst = _inst; } 1302292SN/A 1312683Sktlim@umich.edu /** Returns the current instruction being committed. */ 1322683Sktlim@umich.edu TheISA::MachInst getInst() { return inst; } 1332683Sktlim@umich.edu 1342683Sktlim@umich.edu /** Reads the number of instructions functionally executed and 1352683Sktlim@umich.edu * committed. 1362683Sktlim@umich.edu */ 1372683Sktlim@umich.edu Counter readFuncExeInst() { return funcExeInst; } 1382683Sktlim@umich.edu 1392683Sktlim@umich.edu /** Sets the total number of instructions functionally executed 1402683Sktlim@umich.edu * and committed. 1412683Sktlim@umich.edu */ 1422683Sktlim@umich.edu void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 1432683Sktlim@umich.edu 1442683Sktlim@umich.edu /** Returns the status of this thread. */ 1452683Sktlim@umich.edu Status status() const { return _status; } 1462683Sktlim@umich.edu 1472683Sktlim@umich.edu /** Sets the status of this thread. */ 1482683Sktlim@umich.edu void setStatus(Status new_status) { _status = new_status; } 1492683Sktlim@umich.edu 1503673Srdreslin@umich.edu public: 1513675Sktlim@umich.edu /** Connects port to the functional port of the memory object 1523675Sktlim@umich.edu * below the CPU. */ 1533675Sktlim@umich.edu void connectToMemFunc(Port *port); 1543486Sktlim@umich.edu 1552683Sktlim@umich.edu /** Number of instructions committed. */ 1562683Sktlim@umich.edu Counter numInst; 1572683Sktlim@umich.edu /** Stat for number instructions committed. */ 1582683Sktlim@umich.edu Stats::Scalar<> numInsts; 1592683Sktlim@umich.edu /** Stat for number of memory references. */ 1602683Sktlim@umich.edu Stats::Scalar<> numMemRefs; 1612683Sktlim@umich.edu 1622683Sktlim@umich.edu /** Number of simulated loads, used for tracking events based on 1632683Sktlim@umich.edu * the number of loads committed. 1642683Sktlim@umich.edu */ 1652683Sktlim@umich.edu Counter numLoad; 1662683Sktlim@umich.edu 1672683Sktlim@umich.edu /** The number of simulated loads committed prior to this run. */ 1682683Sktlim@umich.edu Counter startNumLoad; 1692683Sktlim@umich.edu 1702683Sktlim@umich.edu protected: 1712683Sktlim@umich.edu ThreadContext::Status _status; 1722683Sktlim@umich.edu 1733402Sktlim@umich.edu // Pointer to the base CPU. 1743402Sktlim@umich.edu BaseCPU *baseCpu; 1753402Sktlim@umich.edu 1765714Shsul@eecs.umich.edu // system wide HW context id 1775714Shsul@eecs.umich.edu int _contextId; 1785714Shsul@eecs.umich.edu 1792292SN/A // Index of hardware thread context on the CPU that this represents. 1805715Shsul@eecs.umich.edu int _threadId; 1812292SN/A 1822690Sktlim@umich.edu public: 1832683Sktlim@umich.edu /** Last time activate was called on this thread. */ 1842683Sktlim@umich.edu Tick lastActivate; 1852292SN/A 1862683Sktlim@umich.edu /** Last time suspend was called on this thread. */ 1872683Sktlim@umich.edu Tick lastSuspend; 1882292SN/A 1892292SN/A#if FULL_SYSTEM 1902683Sktlim@umich.edu public: 1912292SN/A FunctionProfile *profile; 1922292SN/A ProfileNode *profileNode; 1932292SN/A Addr profilePC; 1942292SN/A EndQuiesceEvent *quiesceEvent; 1952292SN/A 1963548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *kernelStats; 1972683Sktlim@umich.edu protected: 1982683Sktlim@umich.edu /** A functional port outgoing only for functional accesses to physical 1992683Sktlim@umich.edu * addresses.*/ 2002683Sktlim@umich.edu FunctionalPort *physPort; 2012683Sktlim@umich.edu 2022683Sktlim@umich.edu /** A functional port, outgoing only, for functional accesse to virtual 2035497Ssaidi@eecs.umich.edu * addresses. */ 2042683Sktlim@umich.edu VirtualPort *virtPort; 2052292SN/A#else 2062678Sktlim@umich.edu TranslatingPort *port; 2072678Sktlim@umich.edu 2082292SN/A Process *process; 2092292SN/A 2102292SN/A // Address space ID. Note that this is used for TIMING cache 2112292SN/A // simulation only; all functional memory accesses should use 2122292SN/A // one of the FunctionalMemory pointers above. 2132292SN/A short asid; 2142330SN/A 2152330SN/A#endif 2162330SN/A 2172683Sktlim@umich.edu /** Current instruction the thread is committing. Only set and 2182683Sktlim@umich.edu * used for DTB faults currently. 2192683Sktlim@umich.edu */ 2202683Sktlim@umich.edu TheISA::MachInst inst; 2212292SN/A 2223276Sgblack@eecs.umich.edu /** The current microcode pc for the currently executing macro 2233276Sgblack@eecs.umich.edu * operation. 2243276Sgblack@eecs.umich.edu */ 2253276Sgblack@eecs.umich.edu MicroPC microPC; 2263276Sgblack@eecs.umich.edu 2273276Sgblack@eecs.umich.edu /** The next microcode pc for the currently executing macro 2283276Sgblack@eecs.umich.edu * operation. 2293276Sgblack@eecs.umich.edu */ 2303276Sgblack@eecs.umich.edu MicroPC nextMicroPC; 2313276Sgblack@eecs.umich.edu 2322690Sktlim@umich.edu public: 2332292SN/A /** 2342292SN/A * Temporary storage to pass the source address from copy_load to 2352292SN/A * copy_store. 2362292SN/A * @todo Remove this temporary when we have a better way to do it. 2372292SN/A */ 2382292SN/A Addr copySrcAddr; 2392292SN/A /** 2402292SN/A * Temp storage for the physical source address of a copy. 2412292SN/A * @todo Remove this temporary when we have a better way to do it. 2422292SN/A */ 2432292SN/A Addr copySrcPhysAddr; 2442292SN/A 2452292SN/A /* 2462292SN/A * number of executed instructions, for matching with syscall trace 2472292SN/A * points in EIO files. 2482292SN/A */ 2492292SN/A Counter funcExeInst; 2502292SN/A 2512292SN/A // 2522292SN/A // Count failed store conditionals so we can warn of apparent 2532292SN/A // application deadlock situations. 2542292SN/A unsigned storeCondFailures; 2552292SN/A}; 2562292SN/A 2572292SN/A#endif // __CPU_THREAD_STATE_HH__ 258