thread_state.hh revision 3548
12330SN/A/*
22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan
32330SN/A * All rights reserved.
42330SN/A *
52330SN/A * Redistribution and use in source and binary forms, with or without
62330SN/A * modification, are permitted provided that the following conditions are
72330SN/A * met: redistributions of source code must retain the above copyright
82330SN/A * notice, this list of conditions and the following disclaimer;
92330SN/A * redistributions in binary form must reproduce the above copyright
102330SN/A * notice, this list of conditions and the following disclaimer in the
112330SN/A * documentation and/or other materials provided with the distribution;
122330SN/A * neither the name of the copyright holders nor the names of its
132330SN/A * contributors may be used to endorse or promote products derived from
142330SN/A * this software without specific prior written permission.
152330SN/A *
162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272689Sktlim@umich.edu *
282689Sktlim@umich.edu * Authors: Kevin Lim
292330SN/A */
302292SN/A
312292SN/A#ifndef __CPU_THREAD_STATE_HH__
322292SN/A#define __CPU_THREAD_STATE_HH__
332292SN/A
342980Sgblack@eecs.umich.edu#include "arch/types.hh"
352362SN/A#include "cpu/profile.hh"
362680Sktlim@umich.edu#include "cpu/thread_context.hh"
372292SN/A
382678Sktlim@umich.edu#if !FULL_SYSTEM
392683Sktlim@umich.edu#include "mem/mem_object.hh"
402683Sktlim@umich.edu#include "sim/process.hh"
412678Sktlim@umich.edu#endif
422678Sktlim@umich.edu
432292SN/A#if FULL_SYSTEM
442292SN/Aclass EndQuiesceEvent;
452292SN/Aclass FunctionProfile;
462292SN/Aclass ProfileNode;
473548Sgblack@eecs.umich.edunamespace TheISA {
483548Sgblack@eecs.umich.edu    namespace Kernel {
493548Sgblack@eecs.umich.edu        class Statistics;
503548Sgblack@eecs.umich.edu    };
512330SN/A};
522292SN/A#endif
532292SN/A
543402Sktlim@umich.educlass BaseCPU;
552862Sktlim@umich.educlass Checkpoint;
563486Sktlim@umich.educlass Port;
573402Sktlim@umich.educlass TranslatingPort;
582862Sktlim@umich.edu
592330SN/A/**
602330SN/A *  Struct for holding general thread state that is needed across CPU
612330SN/A *  models.  This includes things such as pointers to the process,
622330SN/A *  memory, quiesce events, and certain stats.  This can be expanded
632330SN/A *  to hold more thread-specific stats within it.
642330SN/A */
652292SN/Astruct ThreadState {
662683Sktlim@umich.edu    typedef ThreadContext::Status Status;
672683Sktlim@umich.edu
682292SN/A#if FULL_SYSTEM
693402Sktlim@umich.edu    ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
702292SN/A#else
713402Sktlim@umich.edu    ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
723402Sktlim@umich.edu                short _asid);
732292SN/A#endif
742683Sktlim@umich.edu
753486Sktlim@umich.edu    ~ThreadState();
763486Sktlim@umich.edu
772862Sktlim@umich.edu    void serialize(std::ostream &os);
782862Sktlim@umich.edu
792862Sktlim@umich.edu    void unserialize(Checkpoint *cp, const std::string &section);
802862Sktlim@umich.edu
812683Sktlim@umich.edu    void setCpuId(int id) { cpuId = id; }
822683Sktlim@umich.edu
832683Sktlim@umich.edu    int readCpuId() { return cpuId; }
842683Sktlim@umich.edu
852683Sktlim@umich.edu    void setTid(int id) { tid = id; }
862683Sktlim@umich.edu
872683Sktlim@umich.edu    int readTid() { return tid; }
882683Sktlim@umich.edu
892683Sktlim@umich.edu    Tick readLastActivate() { return lastActivate; }
902683Sktlim@umich.edu
912683Sktlim@umich.edu    Tick readLastSuspend() { return lastSuspend; }
922683Sktlim@umich.edu
932683Sktlim@umich.edu#if FULL_SYSTEM
942683Sktlim@umich.edu    void dumpFuncProfile();
952683Sktlim@umich.edu
962683Sktlim@umich.edu    EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
972683Sktlim@umich.edu
982683Sktlim@umich.edu    void profileClear();
992683Sktlim@umich.edu
1002683Sktlim@umich.edu    void profileSample();
1012683Sktlim@umich.edu
1023548Sgblack@eecs.umich.edu    TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
1032683Sktlim@umich.edu
1042690Sktlim@umich.edu    FunctionalPort *getPhysPort() { return physPort; }
1052690Sktlim@umich.edu
1062683Sktlim@umich.edu    void setPhysPort(FunctionalPort *port) { physPort = port; }
1072683Sktlim@umich.edu
1082690Sktlim@umich.edu    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
1092690Sktlim@umich.edu
1102683Sktlim@umich.edu    void setVirtPort(VirtualPort *port) { virtPort = port; }
1112683Sktlim@umich.edu#else
1122683Sktlim@umich.edu    Process *getProcessPtr() { return process; }
1132683Sktlim@umich.edu
1143402Sktlim@umich.edu    TranslatingPort *getMemPort();
1152683Sktlim@umich.edu
1162683Sktlim@umich.edu    void setMemPort(TranslatingPort *_port) { port = _port; }
1172683Sktlim@umich.edu
1182683Sktlim@umich.edu    int getInstAsid() { return asid; }
1192683Sktlim@umich.edu    int getDataAsid() { return asid; }
1202678Sktlim@umich.edu#endif
1212292SN/A
1222683Sktlim@umich.edu    /** Sets the current instruction being committed. */
1232683Sktlim@umich.edu    void setInst(TheISA::MachInst _inst) { inst = _inst; }
1242292SN/A
1252683Sktlim@umich.edu    /** Returns the current instruction being committed. */
1262683Sktlim@umich.edu    TheISA::MachInst getInst() { return inst; }
1272683Sktlim@umich.edu
1282683Sktlim@umich.edu    /** Reads the number of instructions functionally executed and
1292683Sktlim@umich.edu     * committed.
1302683Sktlim@umich.edu     */
1312683Sktlim@umich.edu    Counter readFuncExeInst() { return funcExeInst; }
1322683Sktlim@umich.edu
1332683Sktlim@umich.edu    /** Sets the total number of instructions functionally executed
1342683Sktlim@umich.edu     * and committed.
1352683Sktlim@umich.edu     */
1362683Sktlim@umich.edu    void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
1372683Sktlim@umich.edu
1382683Sktlim@umich.edu    /** Returns the status of this thread. */
1392683Sktlim@umich.edu    Status status() const { return _status; }
1402683Sktlim@umich.edu
1412683Sktlim@umich.edu    /** Sets the status of this thread. */
1422683Sktlim@umich.edu    void setStatus(Status new_status) { _status = new_status; }
1432683Sktlim@umich.edu
1443486Sktlim@umich.edu  protected:
1453486Sktlim@umich.edu    /** Gets a functional port from the memory object that's connected
1463486Sktlim@umich.edu     * to the CPU. */
1473486Sktlim@umich.edu    Port *getMemFuncPort();
1483486Sktlim@umich.edu
1493486Sktlim@umich.edu  public:
1502683Sktlim@umich.edu    /** Number of instructions committed. */
1512683Sktlim@umich.edu    Counter numInst;
1522683Sktlim@umich.edu    /** Stat for number instructions committed. */
1532683Sktlim@umich.edu    Stats::Scalar<> numInsts;
1542683Sktlim@umich.edu    /** Stat for number of memory references. */
1552683Sktlim@umich.edu    Stats::Scalar<> numMemRefs;
1562683Sktlim@umich.edu
1572683Sktlim@umich.edu    /** Number of simulated loads, used for tracking events based on
1582683Sktlim@umich.edu     * the number of loads committed.
1592683Sktlim@umich.edu     */
1602683Sktlim@umich.edu    Counter numLoad;
1612683Sktlim@umich.edu
1622683Sktlim@umich.edu    /** The number of simulated loads committed prior to this run. */
1632683Sktlim@umich.edu    Counter startNumLoad;
1642683Sktlim@umich.edu
1652683Sktlim@umich.edu  protected:
1662683Sktlim@umich.edu    ThreadContext::Status _status;
1672683Sktlim@umich.edu
1683402Sktlim@umich.edu    // Pointer to the base CPU.
1693402Sktlim@umich.edu    BaseCPU *baseCpu;
1703402Sktlim@umich.edu
1712683Sktlim@umich.edu    // ID of this context w.r.t. the System or Process object to which
1722683Sktlim@umich.edu    // it belongs.  For full-system mode, this is the system CPU ID.
1732292SN/A    int cpuId;
1742292SN/A
1752292SN/A    // Index of hardware thread context on the CPU that this represents.
1762292SN/A    int tid;
1772292SN/A
1782690Sktlim@umich.edu  public:
1792683Sktlim@umich.edu    /** Last time activate was called on this thread. */
1802683Sktlim@umich.edu    Tick lastActivate;
1812292SN/A
1822683Sktlim@umich.edu    /** Last time suspend was called on this thread. */
1832683Sktlim@umich.edu    Tick lastSuspend;
1842292SN/A
1852292SN/A#if FULL_SYSTEM
1862683Sktlim@umich.edu  public:
1872292SN/A    FunctionProfile *profile;
1882292SN/A    ProfileNode *profileNode;
1892292SN/A    Addr profilePC;
1902292SN/A    EndQuiesceEvent *quiesceEvent;
1912292SN/A
1923548Sgblack@eecs.umich.edu    TheISA::Kernel::Statistics *kernelStats;
1932683Sktlim@umich.edu  protected:
1942683Sktlim@umich.edu    /** A functional port outgoing only for functional accesses to physical
1952683Sktlim@umich.edu     * addresses.*/
1962683Sktlim@umich.edu    FunctionalPort *physPort;
1972683Sktlim@umich.edu
1982683Sktlim@umich.edu    /** A functional port, outgoing only, for functional accesse to virtual
1992683Sktlim@umich.edu     * addresses. That doen't require execution context information */
2002683Sktlim@umich.edu    VirtualPort *virtPort;
2012292SN/A#else
2022678Sktlim@umich.edu    TranslatingPort *port;
2032678Sktlim@umich.edu
2042292SN/A    Process *process;
2052292SN/A
2062292SN/A    // Address space ID.  Note that this is used for TIMING cache
2072292SN/A    // simulation only; all functional memory accesses should use
2082292SN/A    // one of the FunctionalMemory pointers above.
2092292SN/A    short asid;
2102330SN/A
2112330SN/A#endif
2122330SN/A
2132683Sktlim@umich.edu    /** Current instruction the thread is committing.  Only set and
2142683Sktlim@umich.edu     * used for DTB faults currently.
2152683Sktlim@umich.edu     */
2162683Sktlim@umich.edu    TheISA::MachInst inst;
2172292SN/A
2183276Sgblack@eecs.umich.edu    /** The current microcode pc for the currently executing macro
2193276Sgblack@eecs.umich.edu     * operation.
2203276Sgblack@eecs.umich.edu     */
2213276Sgblack@eecs.umich.edu    MicroPC microPC;
2223276Sgblack@eecs.umich.edu
2233276Sgblack@eecs.umich.edu    /** The next microcode pc for the currently executing macro
2243276Sgblack@eecs.umich.edu     * operation.
2253276Sgblack@eecs.umich.edu     */
2263276Sgblack@eecs.umich.edu    MicroPC nextMicroPC;
2273276Sgblack@eecs.umich.edu
2282690Sktlim@umich.edu  public:
2292292SN/A    /**
2302292SN/A     * Temporary storage to pass the source address from copy_load to
2312292SN/A     * copy_store.
2322292SN/A     * @todo Remove this temporary when we have a better way to do it.
2332292SN/A     */
2342292SN/A    Addr copySrcAddr;
2352292SN/A    /**
2362292SN/A     * Temp storage for the physical source address of a copy.
2372292SN/A     * @todo Remove this temporary when we have a better way to do it.
2382292SN/A     */
2392292SN/A    Addr copySrcPhysAddr;
2402292SN/A
2412292SN/A    /*
2422292SN/A     * number of executed instructions, for matching with syscall trace
2432292SN/A     * points in EIO files.
2442292SN/A     */
2452292SN/A    Counter funcExeInst;
2462292SN/A
2472292SN/A    //
2482292SN/A    // Count failed store conditionals so we can warn of apparent
2492292SN/A    // application deadlock situations.
2502292SN/A    unsigned storeCondFailures;
2512292SN/A};
2522292SN/A
2532292SN/A#endif // __CPU_THREAD_STATE_HH__
254