thread_state.hh revision 3486
14486Sbinkertn@umich.edu/* 27897Shestness@cs.utexas.edu * Copyright (c) 2006 The Regents of The University of Michigan 34486Sbinkertn@umich.edu * All rights reserved. 44486Sbinkertn@umich.edu * 54486Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64486Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74486Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94486Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114486Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124486Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134486Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144486Sbinkertn@umich.edu * this software without specific prior written permission. 154486Sbinkertn@umich.edu * 164486Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486Sbinkertn@umich.edu * 284486Sbinkertn@umich.edu * Authors: Kevin Lim 297897Shestness@cs.utexas.edu */ 304486Sbinkertn@umich.edu 313102SN/A#ifndef __CPU_THREAD_STATE_HH__ 326654Snate@binkert.org#define __CPU_THREAD_STATE_HH__ 333102SN/A 343102SN/A#include "arch/types.hh" 356654Snate@binkert.org#include "cpu/profile.hh" 3610249Sstephan.diestelhorst@arm.com#include "cpu/thread_context.hh" 378931Sandreas.hansson@arm.com 382212SN/A#if !FULL_SYSTEM 399524SAndreas.Sandberg@ARM.com#include "mem/mem_object.hh" 409524SAndreas.Sandberg@ARM.com#include "sim/process.hh" 412902SN/A#endif 428703Sandreas.hansson@arm.com 431783SN/A#if FULL_SYSTEM 449338SAndreas.Sandberg@arm.comclass EndQuiesceEvent; 458839Sandreas.hansson@arm.comclass FunctionProfile; 467673Snate@binkert.orgclass ProfileNode; 477673Snate@binkert.orgnamespace Kernel { 488597Ssteve.reinhardt@amd.com class Statistics; 498597Ssteve.reinhardt@amd.com}; 508597Ssteve.reinhardt@amd.com#endif 518597Ssteve.reinhardt@amd.com 528597Ssteve.reinhardt@amd.comclass BaseCPU; 538597Ssteve.reinhardt@amd.comclass Checkpoint; 549524SAndreas.Sandberg@ARM.comclass Port; 558597Ssteve.reinhardt@amd.comclass TranslatingPort; 568597Ssteve.reinhardt@amd.com 574859Snate@binkert.org/** 588931Sandreas.hansson@arm.com * Struct for holding general thread state that is needed across CPU 598931Sandreas.hansson@arm.com * models. This includes things such as pointers to the process, 602902SN/A * memory, quiesce events, and certain stats. This can be expanded 619408Sandreas.hansson@arm.com * to hold more thread-specific stats within it. 629408Sandreas.hansson@arm.com */ 639408Sandreas.hansson@arm.comstruct ThreadState { 649408Sandreas.hansson@arm.com typedef ThreadContext::Status Status; 659408Sandreas.hansson@arm.com 669408Sandreas.hansson@arm.com#if FULL_SYSTEM 679814Sandreas.hansson@arm.com ThreadState(BaseCPU *cpu, int _cpuId, int _tid); 689814Sandreas.hansson@arm.com#else 697914SBrad.Beckmann@amd.com ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 708666SPrakash.Ramrakhyani@arm.com short _asid); 717914SBrad.Beckmann@amd.com#endif 727914SBrad.Beckmann@amd.com 737914SBrad.Beckmann@amd.com ~ThreadState(); 747914SBrad.Beckmann@amd.com 757914SBrad.Beckmann@amd.com void serialize(std::ostream &os); 767914SBrad.Beckmann@amd.com 777914SBrad.Beckmann@amd.com void unserialize(Checkpoint *cp, const std::string §ion); 787914SBrad.Beckmann@amd.com 797914SBrad.Beckmann@amd.com void setCpuId(int id) { cpuId = id; } 807914SBrad.Beckmann@amd.com 817914SBrad.Beckmann@amd.com int readCpuId() { return cpuId; } 827914SBrad.Beckmann@amd.com 837914SBrad.Beckmann@amd.com void setTid(int id) { tid = id; } 848769Sgblack@eecs.umich.edu 858769Sgblack@eecs.umich.edu int readTid() { return tid; } 868769Sgblack@eecs.umich.edu 878769Sgblack@eecs.umich.edu Tick readLastActivate() { return lastActivate; } 888769Sgblack@eecs.umich.edu 898769Sgblack@eecs.umich.edu Tick readLastSuspend() { return lastSuspend; } 9010037SARM gem5 Developers 9110037SARM gem5 Developers#if FULL_SYSTEM 9210249Sstephan.diestelhorst@arm.com void dumpFuncProfile(); 9310249Sstephan.diestelhorst@arm.com 9410249Sstephan.diestelhorst@arm.com EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 9510249Sstephan.diestelhorst@arm.com 96 void profileClear(); 97 98 void profileSample(); 99 100 Kernel::Statistics *getKernelStats() { return kernelStats; } 101 102 FunctionalPort *getPhysPort() { return physPort; } 103 104 void setPhysPort(FunctionalPort *port) { physPort = port; } 105 106 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; } 107 108 void setVirtPort(VirtualPort *port) { virtPort = port; } 109#else 110 Process *getProcessPtr() { return process; } 111 112 TranslatingPort *getMemPort(); 113 114 void setMemPort(TranslatingPort *_port) { port = _port; } 115 116 int getInstAsid() { return asid; } 117 int getDataAsid() { return asid; } 118#endif 119 120 /** Sets the current instruction being committed. */ 121 void setInst(TheISA::MachInst _inst) { inst = _inst; } 122 123 /** Returns the current instruction being committed. */ 124 TheISA::MachInst getInst() { return inst; } 125 126 /** Reads the number of instructions functionally executed and 127 * committed. 128 */ 129 Counter readFuncExeInst() { return funcExeInst; } 130 131 /** Sets the total number of instructions functionally executed 132 * and committed. 133 */ 134 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 135 136 /** Returns the status of this thread. */ 137 Status status() const { return _status; } 138 139 /** Sets the status of this thread. */ 140 void setStatus(Status new_status) { _status = new_status; } 141 142 protected: 143 /** Gets a functional port from the memory object that's connected 144 * to the CPU. */ 145 Port *getMemFuncPort(); 146 147 public: 148 /** Number of instructions committed. */ 149 Counter numInst; 150 /** Stat for number instructions committed. */ 151 Stats::Scalar<> numInsts; 152 /** Stat for number of memory references. */ 153 Stats::Scalar<> numMemRefs; 154 155 /** Number of simulated loads, used for tracking events based on 156 * the number of loads committed. 157 */ 158 Counter numLoad; 159 160 /** The number of simulated loads committed prior to this run. */ 161 Counter startNumLoad; 162 163 protected: 164 ThreadContext::Status _status; 165 166 // Pointer to the base CPU. 167 BaseCPU *baseCpu; 168 169 // ID of this context w.r.t. the System or Process object to which 170 // it belongs. For full-system mode, this is the system CPU ID. 171 int cpuId; 172 173 // Index of hardware thread context on the CPU that this represents. 174 int tid; 175 176 public: 177 /** Last time activate was called on this thread. */ 178 Tick lastActivate; 179 180 /** Last time suspend was called on this thread. */ 181 Tick lastSuspend; 182 183#if FULL_SYSTEM 184 public: 185 FunctionProfile *profile; 186 ProfileNode *profileNode; 187 Addr profilePC; 188 EndQuiesceEvent *quiesceEvent; 189 190 Kernel::Statistics *kernelStats; 191 protected: 192 /** A functional port outgoing only for functional accesses to physical 193 * addresses.*/ 194 FunctionalPort *physPort; 195 196 /** A functional port, outgoing only, for functional accesse to virtual 197 * addresses. That doen't require execution context information */ 198 VirtualPort *virtPort; 199#else 200 TranslatingPort *port; 201 202 Process *process; 203 204 // Address space ID. Note that this is used for TIMING cache 205 // simulation only; all functional memory accesses should use 206 // one of the FunctionalMemory pointers above. 207 short asid; 208 209#endif 210 211 /** Current instruction the thread is committing. Only set and 212 * used for DTB faults currently. 213 */ 214 TheISA::MachInst inst; 215 216 /** The current microcode pc for the currently executing macro 217 * operation. 218 */ 219 MicroPC microPC; 220 221 /** The next microcode pc for the currently executing macro 222 * operation. 223 */ 224 MicroPC nextMicroPC; 225 226 public: 227 /** 228 * Temporary storage to pass the source address from copy_load to 229 * copy_store. 230 * @todo Remove this temporary when we have a better way to do it. 231 */ 232 Addr copySrcAddr; 233 /** 234 * Temp storage for the physical source address of a copy. 235 * @todo Remove this temporary when we have a better way to do it. 236 */ 237 Addr copySrcPhysAddr; 238 239 /* 240 * number of executed instructions, for matching with syscall trace 241 * points in EIO files. 242 */ 243 Counter funcExeInst; 244 245 // 246 // Count failed store conditionals so we can warn of apparent 247 // application deadlock situations. 248 unsigned storeCondFailures; 249}; 250 251#endif // __CPU_THREAD_STATE_HH__ 252