thread_state.hh revision 2689
16019Shines@cs.fsu.edu/*
210338SCurtis.Dunham@arm.com * Copyright (c) 2006 The Regents of The University of Michigan
37093Sgblack@eecs.umich.edu * All rights reserved.
47093Sgblack@eecs.umich.edu *
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146019Shines@cs.fsu.edu * this software without specific prior written permission.
156019Shines@cs.fsu.edu *
166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * Authors: Kevin Lim
296019Shines@cs.fsu.edu */
306019Shines@cs.fsu.edu
316019Shines@cs.fsu.edu#ifndef __CPU_THREAD_STATE_HH__
326019Shines@cs.fsu.edu#define __CPU_THREAD_STATE_HH__
336019Shines@cs.fsu.edu
346019Shines@cs.fsu.edu#include "arch/isa_traits.hh"
356019Shines@cs.fsu.edu#include "cpu/thread_context.hh"
366019Shines@cs.fsu.edu
376019Shines@cs.fsu.edu#if !FULL_SYSTEM
386019Shines@cs.fsu.edu#include "mem/mem_object.hh"
396019Shines@cs.fsu.edu#include "mem/translating_port.hh"
406019Shines@cs.fsu.edu#include "sim/process.hh"
416735Sgblack@eecs.umich.edu#endif
426735Sgblack@eecs.umich.edu
4310037SARM gem5 Developers#if FULL_SYSTEM
4410037SARM gem5 Developersclass EndQuiesceEvent;
456019Shines@cs.fsu.educlass FunctionProfile;
466019Shines@cs.fsu.educlass ProfileNode;
476019Shines@cs.fsu.edunamespace Kernel {
4810037SARM gem5 Developers    class Statistics;
4910037SARM gem5 Developers};
5010037SARM gem5 Developers#endif
5110037SARM gem5 Developers
528229Snate@binkert.org/**
538229Snate@binkert.org *  Struct for holding general thread state that is needed across CPU
546019Shines@cs.fsu.edu *  models.  This includes things such as pointers to the process,
558232Snate@binkert.org *  memory, quiesce events, and certain stats.  This can be expanded
568782Sgblack@eecs.umich.edu *  to hold more thread-specific stats within it.
576019Shines@cs.fsu.edu */
586019Shines@cs.fsu.edustruct ThreadState {
596019Shines@cs.fsu.edu    typedef ThreadContext::Status Status;
606019Shines@cs.fsu.edu
6110037SARM gem5 Developers#if FULL_SYSTEM
6210037SARM gem5 Developers    ThreadState(int _cpuId, int _tid);
6310037SARM gem5 Developers#else
6410037SARM gem5 Developers    ThreadState(int _cpuId, int _tid, MemObject *mem,
6510037SARM gem5 Developers                Process *_process, short _asid);
6610037SARM gem5 Developers#endif
6710037SARM gem5 Developers
6810037SARM gem5 Developers    void setCpuId(int id) { cpuId = id; }
6910037SARM gem5 Developers
7010037SARM gem5 Developers    int readCpuId() { return cpuId; }
7110037SARM gem5 Developers
7210037SARM gem5 Developers    void setTid(int id) { tid = id; }
7310037SARM gem5 Developers
7410037SARM gem5 Developers    int readTid() { return tid; }
7510037SARM gem5 Developers
7610037SARM gem5 Developers    Tick readLastActivate() { return lastActivate; }
7710037SARM gem5 Developers
7810037SARM gem5 Developers    Tick readLastSuspend() { return lastSuspend; }
7910037SARM gem5 Developers
8010037SARM gem5 Developers#if FULL_SYSTEM
8110037SARM gem5 Developers    void dumpFuncProfile();
8210037SARM gem5 Developers
8310037SARM gem5 Developers    EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
8410037SARM gem5 Developers
8510037SARM gem5 Developers    void profileClear();
8610037SARM gem5 Developers
8710037SARM gem5 Developers    void profileSample();
8810037SARM gem5 Developers
8910037SARM gem5 Developers    Kernel::Statistics *getKernelStats() { return kernelStats; }
9010037SARM gem5 Developers
9110037SARM gem5 Developers    void setPhysPort(FunctionalPort *port) { physPort = port; }
9210037SARM gem5 Developers
9310037SARM gem5 Developers    void setVirtPort(VirtualPort *port) { virtPort = port; }
9410037SARM gem5 Developers#else
9510037SARM gem5 Developers    Process *getProcessPtr() { return process; }
9610037SARM gem5 Developers
9710037SARM gem5 Developers    TranslatingPort *getMemPort() { return port; }
9810037SARM gem5 Developers
9910037SARM gem5 Developers    void setMemPort(TranslatingPort *_port) { port = _port; }
10010037SARM gem5 Developers
1016019Shines@cs.fsu.edu    int getInstAsid() { return asid; }
10210037SARM gem5 Developers    int getDataAsid() { return asid; }
10310037SARM gem5 Developers#endif
10410037SARM gem5 Developers
1056019Shines@cs.fsu.edu    /** Sets the current instruction being committed. */
10610037SARM gem5 Developers    void setInst(TheISA::MachInst _inst) { inst = _inst; }
10710037SARM gem5 Developers
10810037SARM gem5 Developers    /** Returns the current instruction being committed. */
10910037SARM gem5 Developers    TheISA::MachInst getInst() { return inst; }
11010037SARM gem5 Developers
11110037SARM gem5 Developers    /** Reads the number of instructions functionally executed and
11210037SARM gem5 Developers     * committed.
11310037SARM gem5 Developers     */
11410037SARM gem5 Developers    Counter readFuncExeInst() { return funcExeInst; }
11510037SARM gem5 Developers
11610037SARM gem5 Developers    /** Sets the total number of instructions functionally executed
11710037SARM gem5 Developers     * and committed.
11810037SARM gem5 Developers     */
11910037SARM gem5 Developers    void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
12010037SARM gem5 Developers
12110037SARM gem5 Developers    /** Returns the status of this thread. */
12210037SARM gem5 Developers    Status status() const { return _status; }
12310037SARM gem5 Developers
12410037SARM gem5 Developers    /** Sets the status of this thread. */
12510037SARM gem5 Developers    void setStatus(Status new_status) { _status = new_status; }
12610037SARM gem5 Developers
12710037SARM gem5 Developers    /** Number of instructions committed. */
12810037SARM gem5 Developers    Counter numInst;
12910037SARM gem5 Developers    /** Stat for number instructions committed. */
13010037SARM gem5 Developers    Stats::Scalar<> numInsts;
13110037SARM gem5 Developers    /** Stat for number of memory references. */
13210037SARM gem5 Developers    Stats::Scalar<> numMemRefs;
13310037SARM gem5 Developers
13410037SARM gem5 Developers    /** Number of simulated loads, used for tracking events based on
13510037SARM gem5 Developers     * the number of loads committed.
13610037SARM gem5 Developers     */
13710037SARM gem5 Developers    Counter numLoad;
13810037SARM gem5 Developers
13910037SARM gem5 Developers    /** The number of simulated loads committed prior to this run. */
14010037SARM gem5 Developers    Counter startNumLoad;
14110037SARM gem5 Developers
14210037SARM gem5 Developers  protected:
14310037SARM gem5 Developers    ThreadContext::Status _status;
14410037SARM gem5 Developers
14510037SARM gem5 Developers    // ID of this context w.r.t. the System or Process object to which
1466019Shines@cs.fsu.edu    // it belongs.  For full-system mode, this is the system CPU ID.
14710037SARM gem5 Developers    int cpuId;
14810037SARM gem5 Developers
14910037SARM gem5 Developers    // Index of hardware thread context on the CPU that this represents.
1506019Shines@cs.fsu.edu    int tid;
15110037SARM gem5 Developers
15210037SARM gem5 Developers    /** Last time activate was called on this thread. */
15310037SARM gem5 Developers    Tick lastActivate;
15410037SARM gem5 Developers
15510037SARM gem5 Developers    /** Last time suspend was called on this thread. */
15610037SARM gem5 Developers    Tick lastSuspend;
15710037SARM gem5 Developers
15810037SARM gem5 Developers#if FULL_SYSTEM
15910037SARM gem5 Developers  public:
16010037SARM gem5 Developers    FunctionProfile *profile;
16110037SARM gem5 Developers    ProfileNode *profileNode;
16210037SARM gem5 Developers    Addr profilePC;
16310037SARM gem5 Developers    EndQuiesceEvent *quiesceEvent;
16410037SARM gem5 Developers
16510037SARM gem5 Developers    Kernel::Statistics *kernelStats;
16610037SARM gem5 Developers  protected:
16710037SARM gem5 Developers    /** A functional port outgoing only for functional accesses to physical
16810037SARM gem5 Developers     * addresses.*/
16910037SARM gem5 Developers    FunctionalPort *physPort;
17010037SARM gem5 Developers
17110037SARM gem5 Developers    /** A functional port, outgoing only, for functional accesse to virtual
17210037SARM gem5 Developers     * addresses. That doen't require execution context information */
17310037SARM gem5 Developers    VirtualPort *virtPort;
17410037SARM gem5 Developers#else
17510037SARM gem5 Developers    TranslatingPort *port;
17610037SARM gem5 Developers
17710037SARM gem5 Developers    Process *process;
17810037SARM gem5 Developers
17910037SARM gem5 Developers    // Address space ID.  Note that this is used for TIMING cache
18010037SARM gem5 Developers    // simulation only; all functional memory accesses should use
18110037SARM gem5 Developers    // one of the FunctionalMemory pointers above.
18210037SARM gem5 Developers    short asid;
18310037SARM gem5 Developers#endif
18410037SARM gem5 Developers
18510037SARM gem5 Developers    /** Current instruction the thread is committing.  Only set and
18610037SARM gem5 Developers     * used for DTB faults currently.
18710037SARM gem5 Developers     */
18810037SARM gem5 Developers    TheISA::MachInst inst;
18910037SARM gem5 Developers
19010037SARM gem5 Developers    /**
19110037SARM gem5 Developers     * Temporary storage to pass the source address from copy_load to
1926019Shines@cs.fsu.edu     * copy_store.
19310037SARM gem5 Developers     * @todo Remove this temporary when we have a better way to do it.
19410037SARM gem5 Developers     */
19510037SARM gem5 Developers    Addr copySrcAddr;
1966019Shines@cs.fsu.edu    /**
19710037SARM gem5 Developers     * Temp storage for the physical source address of a copy.
19810037SARM gem5 Developers     * @todo Remove this temporary when we have a better way to do it.
19910037SARM gem5 Developers     */
20010037SARM gem5 Developers    Addr copySrcPhysAddr;
20110037SARM gem5 Developers
20210037SARM gem5 Developers  public:
20310037SARM gem5 Developers    /*
20410037SARM gem5 Developers     * number of executed instructions, for matching with syscall trace
20510037SARM gem5 Developers     * points in EIO files.
20610037SARM gem5 Developers     */
20710037SARM gem5 Developers    Counter funcExeInst;
20810037SARM gem5 Developers
20910037SARM gem5 Developers    //
21010037SARM gem5 Developers    // Count failed store conditionals so we can warn of apparent
21110037SARM gem5 Developers    // application deadlock situations.
21210037SARM gem5 Developers    unsigned storeCondFailures;
21310037SARM gem5 Developers};
21410037SARM gem5 Developers
21510037SARM gem5 Developers#endif // __CPU_THREAD_STATE_HH__
21610037SARM gem5 Developers