thread_state.hh revision 2680
12330SN/A/* 22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272330SN/A */ 282292SN/A 292292SN/A#ifndef __CPU_THREAD_STATE_HH__ 302292SN/A#define __CPU_THREAD_STATE_HH__ 312292SN/A 322680Sktlim@umich.edu#include "cpu/thread_context.hh" 332292SN/A 342678Sktlim@umich.edu#if !FULL_SYSTEM 352678Sktlim@umich.edu#include "mem/translating_port.hh" 362678Sktlim@umich.edu#endif 372678Sktlim@umich.edu 382292SN/A#if FULL_SYSTEM 392292SN/Aclass EndQuiesceEvent; 402292SN/Aclass FunctionProfile; 412292SN/Aclass ProfileNode; 422330SN/Anamespace Kernel { 432330SN/A class Statistics; 442330SN/A}; 452292SN/A#else 462330SN/Aclass FunctionalMemory; 472292SN/Aclass Process; 482292SN/A#endif 492292SN/A 502330SN/A/** 512330SN/A * Struct for holding general thread state that is needed across CPU 522330SN/A * models. This includes things such as pointers to the process, 532330SN/A * memory, quiesce events, and certain stats. This can be expanded 542330SN/A * to hold more thread-specific stats within it. 552330SN/A */ 562292SN/Astruct ThreadState { 572292SN/A#if FULL_SYSTEM 582678Sktlim@umich.edu ThreadState(int _cpuId, int _tid) 592678Sktlim@umich.edu : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 602292SN/A profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL) 612292SN/A#else 622678Sktlim@umich.edu ThreadState(int _cpuId, int _tid, MemObject *mem, 632292SN/A Process *_process, short _asid) 642678Sktlim@umich.edu : cpuId(_cpuId), tid(_tid), process(_process), asid(_asid) 652292SN/A#endif 662292SN/A { 672292SN/A funcExeInst = 0; 682292SN/A storeCondFailures = 0; 692678Sktlim@umich.edu#if !FULL_SYSTEM 702678Sktlim@umich.edu /* Use this port to for syscall emulation writes to memory. */ 712678Sktlim@umich.edu Port *mem_port; 722678Sktlim@umich.edu port = new TranslatingPort(csprintf("%d-funcport", 732678Sktlim@umich.edu tid), 742678Sktlim@umich.edu process->pTable, false); 752678Sktlim@umich.edu mem_port = mem->getPort("functional"); 762678Sktlim@umich.edu mem_port->setPeer(port); 772678Sktlim@umich.edu port->setPeer(mem_port); 782678Sktlim@umich.edu#endif 792292SN/A } 802292SN/A 812680Sktlim@umich.edu ThreadContext::Status status; 822292SN/A 832292SN/A int cpuId; 842292SN/A 852292SN/A // Index of hardware thread context on the CPU that this represents. 862292SN/A int tid; 872292SN/A 882292SN/A Counter numInst; 892292SN/A Stats::Scalar<> numInsts; 902292SN/A Stats::Scalar<> numMemRefs; 912292SN/A 922292SN/A // number of simulated loads 932292SN/A Counter numLoad; 942292SN/A Counter startNumLoad; 952292SN/A 962292SN/A#if FULL_SYSTEM 972292SN/A Tick lastActivate; 982292SN/A Tick lastSuspend; 992292SN/A 1002292SN/A FunctionProfile *profile; 1012292SN/A ProfileNode *profileNode; 1022292SN/A Addr profilePC; 1032292SN/A 1042292SN/A EndQuiesceEvent *quiesceEvent; 1052292SN/A 1062330SN/A Kernel::Statistics *kernelStats; 1072292SN/A#else 1082678Sktlim@umich.edu TranslatingPort *port; 1092678Sktlim@umich.edu 1102292SN/A Process *process; 1112292SN/A 1122292SN/A // Address space ID. Note that this is used for TIMING cache 1132292SN/A // simulation only; all functional memory accesses should use 1142292SN/A // one of the FunctionalMemory pointers above. 1152292SN/A short asid; 1162292SN/A 1172292SN/A#endif 1182292SN/A 1192292SN/A /** 1202292SN/A * Temporary storage to pass the source address from copy_load to 1212292SN/A * copy_store. 1222292SN/A * @todo Remove this temporary when we have a better way to do it. 1232292SN/A */ 1242292SN/A Addr copySrcAddr; 1252292SN/A /** 1262292SN/A * Temp storage for the physical source address of a copy. 1272292SN/A * @todo Remove this temporary when we have a better way to do it. 1282292SN/A */ 1292292SN/A Addr copySrcPhysAddr; 1302292SN/A 1312292SN/A /* 1322292SN/A * number of executed instructions, for matching with syscall trace 1332292SN/A * points in EIO files. 1342292SN/A */ 1352292SN/A Counter funcExeInst; 1362292SN/A 1372292SN/A // 1382292SN/A // Count failed store conditionals so we can warn of apparent 1392292SN/A // application deadlock situations. 1402292SN/A unsigned storeCondFailures; 1412292SN/A}; 1422292SN/A 1432292SN/A#endif // __CPU_THREAD_STATE_HH__ 144