thread_state.cc revision 8799:dac1e33e07b0 
112855Sgabeblack@google.com/*
212855Sgabeblack@google.com * Copyright (c) 2006 The Regents of The University of Michigan
312855Sgabeblack@google.com * All rights reserved.
412855Sgabeblack@google.com *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/kernel_stats.hh"
32#include "base/output.hh"
33#include "cpu/base.hh"
34#include "cpu/profile.hh"
35#include "cpu/quiesce_event.hh"
36#include "cpu/thread_state.hh"
37#include "mem/fs_translating_port_proxy.hh"
38#include "mem/port.hh"
39#include "mem/port_proxy.hh"
40#include "mem/se_translating_port_proxy.hh"
41#include "sim/full_system.hh"
42#include "sim/serialize.hh"
43#include "sim/system.hh"
44
45ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
46    : numInst(0), numLoad(0), _status(ThreadContext::Halted),
47      baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
48      profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
49      kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL),
50      proxy(NULL), funcExeInst(0), storeCondFailures(0)
51{
52}
53
54ThreadState::~ThreadState()
55{
56    if (physProxy != NULL)
57        delete physProxy;
58    if (virtProxy != NULL)
59        delete virtProxy;
60    if (proxy != NULL)
61        delete proxy;
62}
63
64void
65ThreadState::serialize(std::ostream &os)
66{
67    SERIALIZE_ENUM(_status);
68    // thread_num and cpu_id are deterministic from the config
69    SERIALIZE_SCALAR(funcExeInst);
70
71    if (FullSystem) {
72        Tick quiesceEndTick = 0;
73        if (quiesceEvent->scheduled())
74            quiesceEndTick = quiesceEvent->when();
75        SERIALIZE_SCALAR(quiesceEndTick);
76        if (kernelStats)
77            kernelStats->serialize(os);
78    }
79}
80
81void
82ThreadState::unserialize(Checkpoint *cp, const std::string &section)
83{
84
85    UNSERIALIZE_ENUM(_status);
86    // thread_num and cpu_id are deterministic from the config
87    UNSERIALIZE_SCALAR(funcExeInst);
88
89    if (FullSystem) {
90        Tick quiesceEndTick;
91        UNSERIALIZE_SCALAR(quiesceEndTick);
92        if (quiesceEndTick)
93            baseCpu->schedule(quiesceEvent, quiesceEndTick);
94        if (kernelStats)
95            kernelStats->unserialize(cp, section);
96    }
97}
98
99void
100ThreadState::initMemProxies(ThreadContext *tc)
101{
102    // Note that this only refers to the port on the CPU side and can
103    // safely be done at init() time even if the CPU is not connected
104    // (i.e. due to restoring from a checkpoint and later switching
105    // in.
106    if (physProxy == NULL)
107        physProxy = new PortProxy(*baseCpu->getPort("dcache_port"));
108    if (virtProxy == NULL)
109        virtProxy = new FSTranslatingPortProxy(tc);
110}
111
112void
113ThreadState::profileClear()
114{
115    if (profile)
116        profile->clear();
117}
118
119void
120ThreadState::profileSample()
121{
122    if (profile)
123        profile->sample(profileNode, profilePC);
124}
125
126SETranslatingPortProxy *
127ThreadState::getMemProxy()
128{
129    if (proxy != NULL)
130        return proxy;
131
132    /* Use this port proxy to for syscall emulation writes to memory. */
133    proxy = new SETranslatingPortProxy(*process->system->getSystemPort(),
134                                       process,
135                                       SETranslatingPortProxy::NextPage);
136
137    return proxy;
138}
139