thread_state.cc revision 5606
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/output.hh" 32#include "cpu/base.hh" 33#include "cpu/profile.hh" 34#include "cpu/thread_state.hh" 35#include "mem/port.hh" 36#include "mem/translating_port.hh" 37#include "sim/serialize.hh" 38 39#if FULL_SYSTEM 40#include "arch/kernel_stats.hh" 41#include "cpu/quiesce_event.hh" 42#include "mem/vport.hh" 43#endif 44 45#if FULL_SYSTEM 46ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) 47 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 48 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 49 kernelStats(NULL), physPort(NULL), virtPort(NULL), 50 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 51#else 52ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 53 short _asid) 54 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 55 port(NULL), process(_process), asid(_asid), 56 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 57#endif 58{ 59 numInst = 0; 60 numLoad = 0; 61} 62 63ThreadState::~ThreadState() 64{ 65#if !FULL_SYSTEM 66 if (port) { 67 delete port->getPeer(); 68 delete port; 69 } 70#endif 71} 72 73void 74ThreadState::serialize(std::ostream &os) 75{ 76 SERIALIZE_ENUM(_status); 77 // thread_num and cpu_id are deterministic from the config 78 SERIALIZE_SCALAR(funcExeInst); 79 SERIALIZE_SCALAR(inst); 80 SERIALIZE_SCALAR(microPC); 81 SERIALIZE_SCALAR(nextMicroPC); 82 83#if FULL_SYSTEM 84 Tick quiesceEndTick = 0; 85 if (quiesceEvent->scheduled()) 86 quiesceEndTick = quiesceEvent->when(); 87 SERIALIZE_SCALAR(quiesceEndTick); 88 if (kernelStats) 89 kernelStats->serialize(os); 90#endif 91} 92 93void 94ThreadState::unserialize(Checkpoint *cp, const std::string §ion) 95{ 96 97 UNSERIALIZE_ENUM(_status); 98 // thread_num and cpu_id are deterministic from the config 99 UNSERIALIZE_SCALAR(funcExeInst); 100 UNSERIALIZE_SCALAR(inst); 101 UNSERIALIZE_SCALAR(microPC); 102 UNSERIALIZE_SCALAR(nextMicroPC); 103 104#if FULL_SYSTEM 105 Tick quiesceEndTick; 106 UNSERIALIZE_SCALAR(quiesceEndTick); 107 if (quiesceEndTick) 108 baseCpu->schedule(quiesceEvent, quiesceEndTick); 109 if (kernelStats) 110 kernelStats->unserialize(cp, section); 111#endif 112} 113 114#if FULL_SYSTEM 115void 116ThreadState::connectMemPorts(ThreadContext *tc) 117{ 118 connectPhysPort(); 119 connectVirtPort(tc); 120} 121 122void 123ThreadState::connectPhysPort() 124{ 125 // @todo: For now this disregards any older port that may have 126 // already existed. Fix this memory leak once the bus port IDs 127 // for functional ports is resolved. 128 if (physPort) 129 physPort->removeConn(); 130 else 131 physPort = new FunctionalPort(csprintf("%s-%d-funcport", 132 baseCpu->name(), tid)); 133 connectToMemFunc(physPort); 134} 135 136void 137ThreadState::connectVirtPort(ThreadContext *tc) 138{ 139 // @todo: For now this disregards any older port that may have 140 // already existed. Fix this memory leak once the bus port IDs 141 // for functional ports is resolved. 142 if (virtPort) 143 virtPort->removeConn(); 144 else 145 virtPort = new VirtualPort(csprintf("%s-%d-vport", 146 baseCpu->name(), tid), tc); 147 connectToMemFunc(virtPort); 148} 149 150void 151ThreadState::profileClear() 152{ 153 if (profile) 154 profile->clear(); 155} 156 157void 158ThreadState::profileSample() 159{ 160 if (profile) 161 profile->sample(profileNode, profilePC); 162} 163 164#else 165TranslatingPort * 166ThreadState::getMemPort() 167{ 168 if (port != NULL) 169 return port; 170 171 /* Use this port to for syscall emulation writes to memory. */ 172 port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid), 173 process, TranslatingPort::NextPage); 174 175 connectToMemFunc(port); 176 177 return port; 178} 179#endif 180 181void 182ThreadState::connectToMemFunc(Port *port) 183{ 184 Port *dcache_port, *func_mem_port; 185 186 dcache_port = baseCpu->getPort("dcache_port"); 187 assert(dcache_port != NULL); 188 189 MemObject *mem_object = dcache_port->getPeer()->getOwner(); 190 assert(mem_object != NULL); 191 192 func_mem_port = mem_object->getPort("functional"); 193 assert(func_mem_port != NULL); 194 195 func_mem_port->setPeer(port); 196 port->setPeer(func_mem_port); 197} 198