thread_state.cc revision 3565
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/output.hh" 32#include "cpu/base.hh" 33#include "cpu/profile.hh" 34#include "cpu/thread_state.hh" 35#include "mem/port.hh" 36#include "mem/translating_port.hh" 37#include "sim/serialize.hh" 38 39#if FULL_SYSTEM 40#include "arch/kernel_stats.hh" 41#include "cpu/quiesce_event.hh" 42#endif 43 44#if FULL_SYSTEM 45ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) 46 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 47 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 48 physPort(NULL), virtPort(NULL), 49 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 50#else 51ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 52 short _asid) 53 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 54 port(NULL), process(_process), asid(_asid), 55 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 56#endif 57{ 58 numInst = 0; 59 numLoad = 0; 60} 61 62ThreadState::~ThreadState() 63{ 64#if !FULL_SYSTEM 65 if (port) { 66 delete port->getPeer(); 67 delete port; 68 } 69#endif 70} 71 72void 73ThreadState::serialize(std::ostream &os) 74{ 75 SERIALIZE_ENUM(_status); 76 // thread_num and cpu_id are deterministic from the config 77 SERIALIZE_SCALAR(funcExeInst); 78 SERIALIZE_SCALAR(inst); 79 SERIALIZE_SCALAR(microPC); 80 SERIALIZE_SCALAR(nextMicroPC); 81 82#if FULL_SYSTEM 83 Tick quiesceEndTick = 0; 84 if (quiesceEvent->scheduled()) 85 quiesceEndTick = quiesceEvent->when(); 86 SERIALIZE_SCALAR(quiesceEndTick); 87 if (kernelStats) 88 kernelStats->serialize(os); 89#endif 90} 91 92void 93ThreadState::unserialize(Checkpoint *cp, const std::string §ion) 94{ 95 96 UNSERIALIZE_ENUM(_status); 97 // thread_num and cpu_id are deterministic from the config 98 UNSERIALIZE_SCALAR(funcExeInst); 99 UNSERIALIZE_SCALAR(inst); 100 UNSERIALIZE_SCALAR(microPC); 101 UNSERIALIZE_SCALAR(nextMicroPC); 102 103#if FULL_SYSTEM 104 Tick quiesceEndTick; 105 UNSERIALIZE_SCALAR(quiesceEndTick); 106 if (quiesceEndTick) 107 quiesceEvent->schedule(quiesceEndTick); 108 if (kernelStats) 109 kernelStats->unserialize(cp, section); 110#endif 111} 112 113#if FULL_SYSTEM 114 115void 116ThreadState::profileClear() 117{ 118 if (profile) 119 profile->clear(); 120} 121 122void 123ThreadState::profileSample() 124{ 125 if (profile) 126 profile->sample(profileNode, profilePC); 127} 128 129#else 130TranslatingPort * 131ThreadState::getMemPort() 132{ 133 if (port != NULL) 134 return port; 135 136 /* Use this port to for syscall emulation writes to memory. */ 137 port = new TranslatingPort(csprintf("%s-%d-funcport", 138 baseCpu->name(), tid), 139 process->pTable, false); 140 141 Port *func_port = getMemFuncPort(); 142 143 func_port->setPeer(port); 144 port->setPeer(func_port); 145 146 return port; 147} 148#endif 149 150Port * 151ThreadState::getMemFuncPort() 152{ 153 Port *dcache_port, *func_mem_port; 154 155 dcache_port = baseCpu->getPort("dcache_port"); 156 assert(dcache_port != NULL); 157 158 MemObject *mem_object = dcache_port->getPeer()->getOwner(); 159 assert(mem_object != NULL); 160 161 func_mem_port = mem_object->getPort("functional"); 162 assert(func_mem_port != NULL); 163 164 return func_mem_port; 165} 166