thread_state.cc revision 8850
12689Sktlim@umich.edu/* 22689Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32689Sktlim@umich.edu * All rights reserved. 42689Sktlim@umich.edu * 52689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142689Sktlim@umich.edu * this software without specific prior written permission. 152689Sktlim@umich.edu * 162689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu */ 302689Sktlim@umich.edu 318793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 322683Sktlim@umich.edu#include "base/output.hh" 333402Sktlim@umich.edu#include "cpu/base.hh" 342683Sktlim@umich.edu#include "cpu/profile.hh" 358793Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 362683Sktlim@umich.edu#include "cpu/thread_state.hh" 378799Sgblack@eecs.umich.edu#include "mem/fs_translating_port_proxy.hh" 387679Sgblack@eecs.umich.edu#include "mem/port.hh" 398706Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 408706Sandreas.hansson@arm.com#include "mem/se_translating_port_proxy.hh" 418793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 422862Sktlim@umich.edu#include "sim/serialize.hh" 438706Sandreas.hansson@arm.com#include "sim/system.hh" 442862Sktlim@umich.edu 456331Sgblack@eecs.umich.eduThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) 468834Satgutier@umich.edu : numInst(0), numOp(0), numLoad(0), _status(ThreadContext::Halted), 476031Ssteve.reinhardt@amd.com baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0), 482683Sktlim@umich.edu profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 498799Sgblack@eecs.umich.edu kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL), 508799Sgblack@eecs.umich.edu proxy(NULL), funcExeInst(0), storeCondFailures(0) 512683Sktlim@umich.edu{ 522683Sktlim@umich.edu} 532683Sktlim@umich.edu 543486Sktlim@umich.eduThreadState::~ThreadState() 553486Sktlim@umich.edu{ 568799Sgblack@eecs.umich.edu if (physProxy != NULL) 578706Sandreas.hansson@arm.com delete physProxy; 588799Sgblack@eecs.umich.edu if (virtProxy != NULL) 598706Sandreas.hansson@arm.com delete virtProxy; 608799Sgblack@eecs.umich.edu if (proxy != NULL) 618706Sandreas.hansson@arm.com delete proxy; 623486Sktlim@umich.edu} 633486Sktlim@umich.edu 642862Sktlim@umich.eduvoid 652862Sktlim@umich.eduThreadState::serialize(std::ostream &os) 662862Sktlim@umich.edu{ 672862Sktlim@umich.edu SERIALIZE_ENUM(_status); 682862Sktlim@umich.edu // thread_num and cpu_id are deterministic from the config 692862Sktlim@umich.edu SERIALIZE_SCALAR(funcExeInst); 702862Sktlim@umich.edu 718806Sgblack@eecs.umich.edu if (!FullSystem) 728806Sgblack@eecs.umich.edu return; 738806Sgblack@eecs.umich.edu 748806Sgblack@eecs.umich.edu Tick quiesceEndTick = 0; 758806Sgblack@eecs.umich.edu if (quiesceEvent->scheduled()) 768806Sgblack@eecs.umich.edu quiesceEndTick = quiesceEvent->when(); 778806Sgblack@eecs.umich.edu SERIALIZE_SCALAR(quiesceEndTick); 788806Sgblack@eecs.umich.edu if (kernelStats) 798806Sgblack@eecs.umich.edu kernelStats->serialize(os); 802862Sktlim@umich.edu} 812862Sktlim@umich.edu 822862Sktlim@umich.eduvoid 832862Sktlim@umich.eduThreadState::unserialize(Checkpoint *cp, const std::string §ion) 842862Sktlim@umich.edu{ 852862Sktlim@umich.edu 862862Sktlim@umich.edu UNSERIALIZE_ENUM(_status); 872862Sktlim@umich.edu // thread_num and cpu_id are deterministic from the config 882862Sktlim@umich.edu UNSERIALIZE_SCALAR(funcExeInst); 892862Sktlim@umich.edu 908806Sgblack@eecs.umich.edu if (!FullSystem) 918806Sgblack@eecs.umich.edu return; 928806Sgblack@eecs.umich.edu 938806Sgblack@eecs.umich.edu Tick quiesceEndTick; 948806Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(quiesceEndTick); 958806Sgblack@eecs.umich.edu if (quiesceEndTick) 968806Sgblack@eecs.umich.edu baseCpu->schedule(quiesceEvent, quiesceEndTick); 978806Sgblack@eecs.umich.edu if (kernelStats) 988806Sgblack@eecs.umich.edu kernelStats->unserialize(cp, section); 992862Sktlim@umich.edu} 1002862Sktlim@umich.edu 1013675Sktlim@umich.eduvoid 1028706Sandreas.hansson@arm.comThreadState::initMemProxies(ThreadContext *tc) 1033675Sktlim@umich.edu{ 1048706Sandreas.hansson@arm.com // Note that this only refers to the port on the CPU side and can 1058706Sandreas.hansson@arm.com // safely be done at init() time even if the CPU is not connected 1068706Sandreas.hansson@arm.com // (i.e. due to restoring from a checkpoint and later switching 1078706Sandreas.hansson@arm.com // in. 1088706Sandreas.hansson@arm.com if (physProxy == NULL) 1098850Sandreas.hansson@arm.com physProxy = new PortProxy(baseCpu->getDataPort()); 1108706Sandreas.hansson@arm.com if (virtProxy == NULL) 1118706Sandreas.hansson@arm.com virtProxy = new FSTranslatingPortProxy(tc); 1123675Sktlim@umich.edu} 1132683Sktlim@umich.edu 1142683Sktlim@umich.eduvoid 1152683Sktlim@umich.eduThreadState::profileClear() 1162683Sktlim@umich.edu{ 1172683Sktlim@umich.edu if (profile) 1182683Sktlim@umich.edu profile->clear(); 1192683Sktlim@umich.edu} 1202683Sktlim@umich.edu 1212683Sktlim@umich.eduvoid 1222683Sktlim@umich.eduThreadState::profileSample() 1232683Sktlim@umich.edu{ 1242683Sktlim@umich.edu if (profile) 1252683Sktlim@umich.edu profile->sample(profileNode, profilePC); 1262683Sktlim@umich.edu} 1272683Sktlim@umich.edu 1288706Sandreas.hansson@arm.comSETranslatingPortProxy * 1298706Sandreas.hansson@arm.comThreadState::getMemProxy() 1303402Sktlim@umich.edu{ 1318706Sandreas.hansson@arm.com if (proxy != NULL) 1328706Sandreas.hansson@arm.com return proxy; 1333402Sktlim@umich.edu 1348706Sandreas.hansson@arm.com /* Use this port proxy to for syscall emulation writes to memory. */ 1358706Sandreas.hansson@arm.com proxy = new SETranslatingPortProxy(*process->system->getSystemPort(), 1368706Sandreas.hansson@arm.com process, 1378706Sandreas.hansson@arm.com SETranslatingPortProxy::NextPage); 1383402Sktlim@umich.edu 1398706Sandreas.hansson@arm.com return proxy; 1403486Sktlim@umich.edu} 141