thread_state.cc revision 10905
12689Sktlim@umich.edu/* 22689Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32689Sktlim@umich.edu * All rights reserved. 42689Sktlim@umich.edu * 52689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142689Sktlim@umich.edu * this software without specific prior written permission. 152689Sktlim@umich.edu * 162689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu */ 302689Sktlim@umich.edu 318793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 322683Sktlim@umich.edu#include "base/output.hh" 333402Sktlim@umich.edu#include "cpu/base.hh" 342683Sktlim@umich.edu#include "cpu/profile.hh" 358793Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 362683Sktlim@umich.edu#include "cpu/thread_state.hh" 378799Sgblack@eecs.umich.edu#include "mem/fs_translating_port_proxy.hh" 387679Sgblack@eecs.umich.edu#include "mem/port.hh" 398706Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 408706Sandreas.hansson@arm.com#include "mem/se_translating_port_proxy.hh" 418793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 422862Sktlim@umich.edu#include "sim/serialize.hh" 438706Sandreas.hansson@arm.com#include "sim/system.hh" 442862Sktlim@umich.edu 456331Sgblack@eecs.umich.eduThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) 4610537Sandreas.hansson@arm.com : numInst(0), numOp(0), numLoad(0), startNumLoad(0), 4710537Sandreas.hansson@arm.com _status(ThreadContext::Halted), baseCpu(cpu), 4810537Sandreas.hansson@arm.com _contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0), 492683Sktlim@umich.edu profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 508799Sgblack@eecs.umich.edu kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL), 518799Sgblack@eecs.umich.edu proxy(NULL), funcExeInst(0), storeCondFailures(0) 522683Sktlim@umich.edu{ 532683Sktlim@umich.edu} 542683Sktlim@umich.edu 553486Sktlim@umich.eduThreadState::~ThreadState() 563486Sktlim@umich.edu{ 578799Sgblack@eecs.umich.edu if (physProxy != NULL) 588706Sandreas.hansson@arm.com delete physProxy; 598799Sgblack@eecs.umich.edu if (virtProxy != NULL) 608706Sandreas.hansson@arm.com delete virtProxy; 618799Sgblack@eecs.umich.edu if (proxy != NULL) 628706Sandreas.hansson@arm.com delete proxy; 633486Sktlim@umich.edu} 643486Sktlim@umich.edu 652862Sktlim@umich.eduvoid 6610905Sandreas.sandberg@arm.comThreadState::serialize(CheckpointOut &cp) const 672862Sktlim@umich.edu{ 682862Sktlim@umich.edu SERIALIZE_ENUM(_status); 692862Sktlim@umich.edu // thread_num and cpu_id are deterministic from the config 702862Sktlim@umich.edu SERIALIZE_SCALAR(funcExeInst); 712862Sktlim@umich.edu 728806Sgblack@eecs.umich.edu if (!FullSystem) 738806Sgblack@eecs.umich.edu return; 748806Sgblack@eecs.umich.edu 758806Sgblack@eecs.umich.edu Tick quiesceEndTick = 0; 768806Sgblack@eecs.umich.edu if (quiesceEvent->scheduled()) 778806Sgblack@eecs.umich.edu quiesceEndTick = quiesceEvent->when(); 788806Sgblack@eecs.umich.edu SERIALIZE_SCALAR(quiesceEndTick); 798806Sgblack@eecs.umich.edu if (kernelStats) 8010905Sandreas.sandberg@arm.com kernelStats->serialize(cp); 812862Sktlim@umich.edu} 822862Sktlim@umich.edu 832862Sktlim@umich.eduvoid 8410905Sandreas.sandberg@arm.comThreadState::unserialize(CheckpointIn &cp) 852862Sktlim@umich.edu{ 862862Sktlim@umich.edu 872862Sktlim@umich.edu UNSERIALIZE_ENUM(_status); 882862Sktlim@umich.edu // thread_num and cpu_id are deterministic from the config 892862Sktlim@umich.edu UNSERIALIZE_SCALAR(funcExeInst); 902862Sktlim@umich.edu 918806Sgblack@eecs.umich.edu if (!FullSystem) 928806Sgblack@eecs.umich.edu return; 938806Sgblack@eecs.umich.edu 948806Sgblack@eecs.umich.edu Tick quiesceEndTick; 958806Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(quiesceEndTick); 968806Sgblack@eecs.umich.edu if (quiesceEndTick) 978806Sgblack@eecs.umich.edu baseCpu->schedule(quiesceEvent, quiesceEndTick); 988806Sgblack@eecs.umich.edu if (kernelStats) 9910905Sandreas.sandberg@arm.com kernelStats->unserialize(cp); 1002862Sktlim@umich.edu} 1012862Sktlim@umich.edu 1023675Sktlim@umich.eduvoid 1038706Sandreas.hansson@arm.comThreadState::initMemProxies(ThreadContext *tc) 1043675Sktlim@umich.edu{ 1058921Sandreas.hansson@arm.com // The port proxies only refer to the data port on the CPU side 1068921Sandreas.hansson@arm.com // and can safely be done at init() time even if the CPU is not 1078921Sandreas.hansson@arm.com // connected, i.e. when restoring from a checkpoint and later 1088921Sandreas.hansson@arm.com // switching the CPU in. 1098921Sandreas.hansson@arm.com if (FullSystem) { 1108921Sandreas.hansson@arm.com assert(physProxy == NULL); 1118921Sandreas.hansson@arm.com // This cannot be done in the constructor as the thread state 1128852Sandreas.hansson@arm.com // itself is created in the base cpu constructor and the 1138921Sandreas.hansson@arm.com // getDataPort is a virtual function 1149814Sandreas.hansson@arm.com physProxy = new PortProxy(baseCpu->getDataPort(), 1159814Sandreas.hansson@arm.com baseCpu->cacheLineSize()); 1168921Sandreas.hansson@arm.com 1178921Sandreas.hansson@arm.com assert(virtProxy == NULL); 1188706Sandreas.hansson@arm.com virtProxy = new FSTranslatingPortProxy(tc); 1198921Sandreas.hansson@arm.com } else { 1208921Sandreas.hansson@arm.com assert(proxy == NULL); 1218921Sandreas.hansson@arm.com proxy = new SETranslatingPortProxy(baseCpu->getDataPort(), 1228921Sandreas.hansson@arm.com process, 1238921Sandreas.hansson@arm.com SETranslatingPortProxy::NextPage); 1248921Sandreas.hansson@arm.com } 1253675Sktlim@umich.edu} 1262683Sktlim@umich.edu 1279101SBrad.Beckmann@amd.comPortProxy & 1289101SBrad.Beckmann@amd.comThreadState::getPhysProxy() 1299101SBrad.Beckmann@amd.com{ 1309101SBrad.Beckmann@amd.com assert(FullSystem); 1319101SBrad.Beckmann@amd.com assert(physProxy != NULL); 1329101SBrad.Beckmann@amd.com return *physProxy; 1339101SBrad.Beckmann@amd.com} 1349101SBrad.Beckmann@amd.com 1359101SBrad.Beckmann@amd.comFSTranslatingPortProxy & 1369101SBrad.Beckmann@amd.comThreadState::getVirtProxy() 1379101SBrad.Beckmann@amd.com{ 1389101SBrad.Beckmann@amd.com assert(FullSystem); 1399101SBrad.Beckmann@amd.com assert(virtProxy != NULL); 1409101SBrad.Beckmann@amd.com return *virtProxy; 1419101SBrad.Beckmann@amd.com} 1429101SBrad.Beckmann@amd.com 1439101SBrad.Beckmann@amd.comSETranslatingPortProxy & 1449101SBrad.Beckmann@amd.comThreadState::getMemProxy() 1459101SBrad.Beckmann@amd.com{ 1469101SBrad.Beckmann@amd.com assert(!FullSystem); 1479101SBrad.Beckmann@amd.com assert(proxy != NULL); 1489101SBrad.Beckmann@amd.com return *proxy; 1499101SBrad.Beckmann@amd.com} 1509101SBrad.Beckmann@amd.com 1512683Sktlim@umich.eduvoid 1522683Sktlim@umich.eduThreadState::profileClear() 1532683Sktlim@umich.edu{ 1542683Sktlim@umich.edu if (profile) 1552683Sktlim@umich.edu profile->clear(); 1562683Sktlim@umich.edu} 1572683Sktlim@umich.edu 1582683Sktlim@umich.eduvoid 1592683Sktlim@umich.eduThreadState::profileSample() 1602683Sktlim@umich.edu{ 1612683Sktlim@umich.edu if (profile) 1622683Sktlim@umich.edu profile->sample(profileNode, profilePC); 1632683Sktlim@umich.edu} 164