thread_context.hh revision 9920:028e4da64b42
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54
55// @todo: Figure out a more architecture independent way to obtain the ITB and
56// DTB pointers.
57namespace TheISA
58{
59    class Decoder;
60    class TLB;
61}
62class BaseCPU;
63class CheckerCPU;
64class Checkpoint;
65class EndQuiesceEvent;
66class SETranslatingPortProxy;
67class FSTranslatingPortProxy;
68class PortProxy;
69class Process;
70class System;
71namespace TheISA {
72    namespace Kernel {
73        class Statistics;
74    }
75}
76
77/**
78 * ThreadContext is the external interface to all thread state for
79 * anything outside of the CPU. It provides all accessor methods to
80 * state that might be needed by external objects, ranging from
81 * register values to things such as kernel stats. It is an abstract
82 * base class; the CPU can create its own ThreadContext by either
83 * deriving from it, or using the templated ProxyThreadContext.
84 *
85 * The ThreadContext is slightly different than the ExecContext.  The
86 * ThreadContext provides access to an individual thread's state; an
87 * ExecContext provides ISA access to the CPU (meaning it is
88 * implicitly multithreaded on SMT systems).  Additionally the
89 * ThreadState is an abstract class that exactly defines the
90 * interface; the ExecContext is a more implicit interface that must
91 * be implemented so that the ISA can access whatever state it needs.
92 */
93class ThreadContext
94{
95  protected:
96    typedef TheISA::MachInst MachInst;
97    typedef TheISA::IntReg IntReg;
98    typedef TheISA::FloatReg FloatReg;
99    typedef TheISA::FloatRegBits FloatRegBits;
100    typedef TheISA::CCReg CCReg;
101    typedef TheISA::MiscReg MiscReg;
102  public:
103
104    enum Status
105    {
106        /// Running.  Instructions should be executed only when
107        /// the context is in this state.
108        Active,
109
110        /// Temporarily inactive.  Entered while waiting for
111        /// synchronization, etc.
112        Suspended,
113
114        /// Permanently shut down.  Entered when target executes
115        /// m5exit pseudo-instruction.  When all contexts enter
116        /// this state, the simulation will terminate.
117        Halted
118    };
119
120    virtual ~ThreadContext() { };
121
122    virtual BaseCPU *getCpuPtr() = 0;
123
124    virtual int cpuId() = 0;
125
126    virtual int threadId() = 0;
127
128    virtual void setThreadId(int id) = 0;
129
130    virtual int contextId() = 0;
131
132    virtual void setContextId(int id) = 0;
133
134    virtual TheISA::TLB *getITBPtr() = 0;
135
136    virtual TheISA::TLB *getDTBPtr() = 0;
137
138    virtual CheckerCPU *getCheckerCpuPtr() = 0;
139
140    virtual TheISA::Decoder *getDecoderPtr() = 0;
141
142    virtual System *getSystemPtr() = 0;
143
144    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
145
146    virtual PortProxy &getPhysProxy() = 0;
147
148    virtual FSTranslatingPortProxy &getVirtProxy() = 0;
149
150    /**
151     * Initialise the physical and virtual port proxies and tie them to
152     * the data port of the CPU.
153     *
154     * tc ThreadContext for the virtual-to-physical translation
155     */
156    virtual void initMemProxies(ThreadContext *tc) = 0;
157
158    virtual SETranslatingPortProxy &getMemProxy() = 0;
159
160    virtual Process *getProcessPtr() = 0;
161
162    virtual Status status() const = 0;
163
164    virtual void setStatus(Status new_status) = 0;
165
166    /// Set the status to Active.  Optional delay indicates number of
167    /// cycles to wait before beginning execution.
168    virtual void activate(Cycles delay = Cycles(1)) = 0;
169
170    /// Set the status to Suspended.
171    virtual void suspend(Cycles delay = Cycles(0)) = 0;
172
173    /// Set the status to Halted.
174    virtual void halt(Cycles delay = Cycles(0)) = 0;
175
176    virtual void dumpFuncProfile() = 0;
177
178    virtual void takeOverFrom(ThreadContext *old_context) = 0;
179
180    virtual void regStats(const std::string &name) = 0;
181
182    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
183
184    // Not necessarily the best location for these...
185    // Having an extra function just to read these is obnoxious
186    virtual Tick readLastActivate() = 0;
187    virtual Tick readLastSuspend() = 0;
188
189    virtual void profileClear() = 0;
190    virtual void profileSample() = 0;
191
192    virtual void copyArchRegs(ThreadContext *tc) = 0;
193
194    virtual void clearArchRegs() = 0;
195
196    //
197    // New accessors for new decoder.
198    //
199    virtual uint64_t readIntReg(int reg_idx) = 0;
200
201    virtual FloatReg readFloatReg(int reg_idx) = 0;
202
203    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
204
205    virtual CCReg readCCReg(int reg_idx) = 0;
206
207    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
208
209    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
210
211    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
212
213    virtual void setCCReg(int reg_idx, CCReg val) = 0;
214
215    virtual TheISA::PCState pcState() = 0;
216
217    virtual void pcState(const TheISA::PCState &val) = 0;
218
219    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
220
221    virtual Addr instAddr() = 0;
222
223    virtual Addr nextInstAddr() = 0;
224
225    virtual MicroPC microPC() = 0;
226
227    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
228
229    virtual MiscReg readMiscReg(int misc_reg) = 0;
230
231    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
232
233    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
234
235    virtual int flattenIntIndex(int reg) = 0;
236    virtual int flattenFloatIndex(int reg) = 0;
237    virtual int flattenCCIndex(int reg) = 0;
238
239    virtual uint64_t
240    readRegOtherThread(int misc_reg, ThreadID tid)
241    {
242        return 0;
243    }
244
245    virtual void
246    setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
247    {
248    }
249
250    // Also not necessarily the best location for these two.  Hopefully will go
251    // away once we decide upon where st cond failures goes.
252    virtual unsigned readStCondFailures() = 0;
253
254    virtual void setStCondFailures(unsigned sc_failures) = 0;
255
256    // Only really makes sense for old CPU model.  Still could be useful though.
257    virtual bool misspeculating() = 0;
258
259    // Same with st cond failures.
260    virtual Counter readFuncExeInst() = 0;
261
262    virtual void syscall(int64_t callnum) = 0;
263
264    // This function exits the thread context in the CPU and returns
265    // 1 if the CPU has no more active threads (meaning it's OK to exit);
266    // Used in syscall-emulation mode when a  thread calls the exit syscall.
267    virtual int exit() { return 1; };
268
269    /** function to compare two thread contexts (for debugging) */
270    static void compare(ThreadContext *one, ThreadContext *two);
271
272    /** @{ */
273    /**
274     * Flat register interfaces
275     *
276     * Some architectures have different registers visible in
277     * different modes. Such architectures "flatten" a register (see
278     * flattenIntIndex() and flattenFloatIndex()) to map it into the
279     * gem5 register file. This interface provides a flat interface to
280     * the underlying register file, which allows for example
281     * serialization code to access all registers.
282     */
283
284    virtual uint64_t readIntRegFlat(int idx) = 0;
285    virtual void setIntRegFlat(int idx, uint64_t val) = 0;
286
287    virtual FloatReg readFloatRegFlat(int idx) = 0;
288    virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
289
290    virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
291    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
292
293    virtual CCReg readCCRegFlat(int idx) = 0;
294    virtual void setCCRegFlat(int idx, CCReg val) = 0;
295    /** @} */
296
297};
298
299/**
300 * ProxyThreadContext class that provides a way to implement a
301 * ThreadContext without having to derive from it. ThreadContext is an
302 * abstract class, so anything that derives from it and uses its
303 * interface will pay the overhead of virtual function calls.  This
304 * class is created to enable a user-defined Thread object to be used
305 * wherever ThreadContexts are used, without paying the overhead of
306 * virtual function calls when it is used by itself.  See
307 * simple_thread.hh for an example of this.
308 */
309template <class TC>
310class ProxyThreadContext : public ThreadContext
311{
312  public:
313    ProxyThreadContext(TC *actual_tc)
314    { actualTC = actual_tc; }
315
316  private:
317    TC *actualTC;
318
319  public:
320
321    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
322
323    int cpuId() { return actualTC->cpuId(); }
324
325    int threadId() { return actualTC->threadId(); }
326
327    void setThreadId(int id) { return actualTC->setThreadId(id); }
328
329    int contextId() { return actualTC->contextId(); }
330
331    void setContextId(int id) { actualTC->setContextId(id); }
332
333    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
334
335    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
336
337    CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
338
339    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
340
341    System *getSystemPtr() { return actualTC->getSystemPtr(); }
342
343    TheISA::Kernel::Statistics *getKernelStats()
344    { return actualTC->getKernelStats(); }
345
346    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
347
348    FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
349
350    void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
351
352    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
353
354    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
355
356    Status status() const { return actualTC->status(); }
357
358    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
359
360    /// Set the status to Active.  Optional delay indicates number of
361    /// cycles to wait before beginning execution.
362    void activate(Cycles delay = Cycles(1))
363    { actualTC->activate(delay); }
364
365    /// Set the status to Suspended.
366    void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
367
368    /// Set the status to Halted.
369    void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
370
371    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
372
373    void takeOverFrom(ThreadContext *oldContext)
374    { actualTC->takeOverFrom(oldContext); }
375
376    void regStats(const std::string &name) { actualTC->regStats(name); }
377
378    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
379
380    Tick readLastActivate() { return actualTC->readLastActivate(); }
381    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
382
383    void profileClear() { return actualTC->profileClear(); }
384    void profileSample() { return actualTC->profileSample(); }
385
386    // @todo: Do I need this?
387    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
388
389    void clearArchRegs() { actualTC->clearArchRegs(); }
390
391    //
392    // New accessors for new decoder.
393    //
394    uint64_t readIntReg(int reg_idx)
395    { return actualTC->readIntReg(reg_idx); }
396
397    FloatReg readFloatReg(int reg_idx)
398    { return actualTC->readFloatReg(reg_idx); }
399
400    FloatRegBits readFloatRegBits(int reg_idx)
401    { return actualTC->readFloatRegBits(reg_idx); }
402
403    CCReg readCCReg(int reg_idx)
404    { return actualTC->readCCReg(reg_idx); }
405
406    void setIntReg(int reg_idx, uint64_t val)
407    { actualTC->setIntReg(reg_idx, val); }
408
409    void setFloatReg(int reg_idx, FloatReg val)
410    { actualTC->setFloatReg(reg_idx, val); }
411
412    void setFloatRegBits(int reg_idx, FloatRegBits val)
413    { actualTC->setFloatRegBits(reg_idx, val); }
414
415    void setCCReg(int reg_idx, CCReg val)
416    { actualTC->setCCReg(reg_idx, val); }
417
418    TheISA::PCState pcState() { return actualTC->pcState(); }
419
420    void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
421
422    void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
423
424    Addr instAddr() { return actualTC->instAddr(); }
425    Addr nextInstAddr() { return actualTC->nextInstAddr(); }
426    MicroPC microPC() { return actualTC->microPC(); }
427
428    bool readPredicate() { return actualTC->readPredicate(); }
429
430    void setPredicate(bool val)
431    { actualTC->setPredicate(val); }
432
433    MiscReg readMiscRegNoEffect(int misc_reg)
434    { return actualTC->readMiscRegNoEffect(misc_reg); }
435
436    MiscReg readMiscReg(int misc_reg)
437    { return actualTC->readMiscReg(misc_reg); }
438
439    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
440    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
441
442    void setMiscReg(int misc_reg, const MiscReg &val)
443    { return actualTC->setMiscReg(misc_reg, val); }
444
445    int flattenIntIndex(int reg)
446    { return actualTC->flattenIntIndex(reg); }
447
448    int flattenFloatIndex(int reg)
449    { return actualTC->flattenFloatIndex(reg); }
450
451    int flattenCCIndex(int reg)
452    { return actualTC->flattenCCIndex(reg); }
453
454    unsigned readStCondFailures()
455    { return actualTC->readStCondFailures(); }
456
457    void setStCondFailures(unsigned sc_failures)
458    { actualTC->setStCondFailures(sc_failures); }
459
460    // @todo: Fix this!
461    bool misspeculating() { return actualTC->misspeculating(); }
462
463    void syscall(int64_t callnum)
464    { actualTC->syscall(callnum); }
465
466    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
467
468    uint64_t readIntRegFlat(int idx)
469    { return actualTC->readIntRegFlat(idx); }
470
471    void setIntRegFlat(int idx, uint64_t val)
472    { actualTC->setIntRegFlat(idx, val); }
473
474    FloatReg readFloatRegFlat(int idx)
475    { return actualTC->readFloatRegFlat(idx); }
476
477    void setFloatRegFlat(int idx, FloatReg val)
478    { actualTC->setFloatRegFlat(idx, val); }
479
480    FloatRegBits readFloatRegBitsFlat(int idx)
481    { return actualTC->readFloatRegBitsFlat(idx); }
482
483    void setFloatRegBitsFlat(int idx, FloatRegBits val)
484    { actualTC->setFloatRegBitsFlat(idx, val); }
485
486    CCReg readCCRegFlat(int idx)
487    { return actualTC->readCCRegFlat(idx); }
488
489    void setCCRegFlat(int idx, CCReg val)
490    { actualTC->setCCRegFlat(idx, val); }
491};
492
493/** @{ */
494/**
495 * Thread context serialization helpers
496 *
497 * These helper functions provide a way to the data in a
498 * ThreadContext. They are provided as separate helper function since
499 * implementing them as members of the ThreadContext interface would
500 * be confusing when the ThreadContext is exported via a proxy.
501 */
502
503void serialize(ThreadContext &tc, std::ostream &os);
504void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section);
505
506/** @} */
507
508
509/**
510 * Copy state between thread contexts in preparation for CPU handover.
511 *
512 * @note This method modifies the old thread contexts as well as the
513 * new thread context. The old thread context will have its quiesce
514 * event descheduled if it is scheduled and its status set to halted.
515 *
516 * @param new_tc Destination ThreadContext.
517 * @param old_tc Source ThreadContext.
518 */
519void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
520
521#endif
522