thread_context.hh revision 9426
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_THREAD_CONTEXT_HH__ 44#define __CPU_THREAD_CONTEXT_HH__ 45 46#include <iostream> 47#include <string> 48 49#include "arch/registers.hh" 50#include "arch/types.hh" 51#include "base/types.hh" 52#include "config/the_isa.hh" 53 54// @todo: Figure out a more architecture independent way to obtain the ITB and 55// DTB pointers. 56namespace TheISA 57{ 58 class Decoder; 59 class TLB; 60} 61class BaseCPU; 62class CheckerCPU; 63class Checkpoint; 64class EndQuiesceEvent; 65class SETranslatingPortProxy; 66class FSTranslatingPortProxy; 67class PortProxy; 68class Process; 69class System; 70namespace TheISA { 71 namespace Kernel { 72 class Statistics; 73 } 74} 75 76/** 77 * ThreadContext is the external interface to all thread state for 78 * anything outside of the CPU. It provides all accessor methods to 79 * state that might be needed by external objects, ranging from 80 * register values to things such as kernel stats. It is an abstract 81 * base class; the CPU can create its own ThreadContext by either 82 * deriving from it, or using the templated ProxyThreadContext. 83 * 84 * The ThreadContext is slightly different than the ExecContext. The 85 * ThreadContext provides access to an individual thread's state; an 86 * ExecContext provides ISA access to the CPU (meaning it is 87 * implicitly multithreaded on SMT systems). Additionally the 88 * ThreadState is an abstract class that exactly defines the 89 * interface; the ExecContext is a more implicit interface that must 90 * be implemented so that the ISA can access whatever state it needs. 91 */ 92class ThreadContext 93{ 94 protected: 95 typedef TheISA::MachInst MachInst; 96 typedef TheISA::IntReg IntReg; 97 typedef TheISA::FloatReg FloatReg; 98 typedef TheISA::FloatRegBits FloatRegBits; 99 typedef TheISA::MiscReg MiscReg; 100 public: 101 102 enum Status 103 { 104 /// Running. Instructions should be executed only when 105 /// the context is in this state. 106 Active, 107 108 /// Temporarily inactive. Entered while waiting for 109 /// synchronization, etc. 110 Suspended, 111 112 /// Permanently shut down. Entered when target executes 113 /// m5exit pseudo-instruction. When all contexts enter 114 /// this state, the simulation will terminate. 115 Halted 116 }; 117 118 virtual ~ThreadContext() { }; 119 120 virtual BaseCPU *getCpuPtr() = 0; 121 122 virtual int cpuId() = 0; 123 124 virtual int threadId() = 0; 125 126 virtual void setThreadId(int id) = 0; 127 128 virtual int contextId() = 0; 129 130 virtual void setContextId(int id) = 0; 131 132 virtual TheISA::TLB *getITBPtr() = 0; 133 134 virtual TheISA::TLB *getDTBPtr() = 0; 135 136 virtual CheckerCPU *getCheckerCpuPtr() = 0; 137 138 virtual TheISA::Decoder *getDecoderPtr() = 0; 139 140 virtual System *getSystemPtr() = 0; 141 142 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 143 144 virtual PortProxy &getPhysProxy() = 0; 145 146 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 147 148 /** 149 * Initialise the physical and virtual port proxies and tie them to 150 * the data port of the CPU. 151 * 152 * tc ThreadContext for the virtual-to-physical translation 153 */ 154 virtual void initMemProxies(ThreadContext *tc) = 0; 155 156 virtual SETranslatingPortProxy &getMemProxy() = 0; 157 158 virtual Process *getProcessPtr() = 0; 159 160 virtual Status status() const = 0; 161 162 virtual void setStatus(Status new_status) = 0; 163 164 /// Set the status to Active. Optional delay indicates number of 165 /// cycles to wait before beginning execution. 166 virtual void activate(Cycles delay = Cycles(1)) = 0; 167 168 /// Set the status to Suspended. 169 virtual void suspend(Cycles delay = Cycles(0)) = 0; 170 171 /// Set the status to Halted. 172 virtual void halt(Cycles delay = Cycles(0)) = 0; 173 174 virtual void dumpFuncProfile() = 0; 175 176 virtual void takeOverFrom(ThreadContext *old_context) = 0; 177 178 virtual void regStats(const std::string &name) = 0; 179 180 virtual void serialize(std::ostream &os) = 0; 181 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 182 183 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 184 185 // Not necessarily the best location for these... 186 // Having an extra function just to read these is obnoxious 187 virtual Tick readLastActivate() = 0; 188 virtual Tick readLastSuspend() = 0; 189 190 virtual void profileClear() = 0; 191 virtual void profileSample() = 0; 192 193 virtual void copyArchRegs(ThreadContext *tc) = 0; 194 195 virtual void clearArchRegs() = 0; 196 197 // 198 // New accessors for new decoder. 199 // 200 virtual uint64_t readIntReg(int reg_idx) = 0; 201 202 virtual FloatReg readFloatReg(int reg_idx) = 0; 203 204 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 205 206 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 207 208 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 209 210 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 211 212 virtual TheISA::PCState pcState() = 0; 213 214 virtual void pcState(const TheISA::PCState &val) = 0; 215 216 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 217 218 virtual Addr instAddr() = 0; 219 220 virtual Addr nextInstAddr() = 0; 221 222 virtual MicroPC microPC() = 0; 223 224 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 225 226 virtual MiscReg readMiscReg(int misc_reg) = 0; 227 228 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 229 230 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 231 232 virtual int flattenIntIndex(int reg) = 0; 233 virtual int flattenFloatIndex(int reg) = 0; 234 235 virtual uint64_t 236 readRegOtherThread(int misc_reg, ThreadID tid) 237 { 238 return 0; 239 } 240 241 virtual void 242 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 243 { 244 } 245 246 // Also not necessarily the best location for these two. Hopefully will go 247 // away once we decide upon where st cond failures goes. 248 virtual unsigned readStCondFailures() = 0; 249 250 virtual void setStCondFailures(unsigned sc_failures) = 0; 251 252 // Only really makes sense for old CPU model. Still could be useful though. 253 virtual bool misspeculating() = 0; 254 255 // Same with st cond failures. 256 virtual Counter readFuncExeInst() = 0; 257 258 virtual void syscall(int64_t callnum) = 0; 259 260 // This function exits the thread context in the CPU and returns 261 // 1 if the CPU has no more active threads (meaning it's OK to exit); 262 // Used in syscall-emulation mode when a thread calls the exit syscall. 263 virtual int exit() { return 1; }; 264 265 /** function to compare two thread contexts (for debugging) */ 266 static void compare(ThreadContext *one, ThreadContext *two); 267 268 /** @{ */ 269 /** 270 * Flat register interfaces 271 * 272 * Some architectures have different registers visible in 273 * different modes. Such architectures "flatten" a register (see 274 * flattenIntIndex() and flattenFloatIndex()) to map it into the 275 * gem5 register file. This interface provides a flat interface to 276 * the underlying register file, which allows for example 277 * serialization code to access all registers. 278 */ 279 280 virtual uint64_t readIntRegFlat(int idx) = 0; 281 virtual void setIntRegFlat(int idx, uint64_t val) = 0; 282 283 virtual FloatReg readFloatRegFlat(int idx) = 0; 284 virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 285 286 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 287 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 288 289 /** @} */ 290 291}; 292 293/** 294 * ProxyThreadContext class that provides a way to implement a 295 * ThreadContext without having to derive from it. ThreadContext is an 296 * abstract class, so anything that derives from it and uses its 297 * interface will pay the overhead of virtual function calls. This 298 * class is created to enable a user-defined Thread object to be used 299 * wherever ThreadContexts are used, without paying the overhead of 300 * virtual function calls when it is used by itself. See 301 * simple_thread.hh for an example of this. 302 */ 303template <class TC> 304class ProxyThreadContext : public ThreadContext 305{ 306 public: 307 ProxyThreadContext(TC *actual_tc) 308 { actualTC = actual_tc; } 309 310 private: 311 TC *actualTC; 312 313 public: 314 315 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 316 317 int cpuId() { return actualTC->cpuId(); } 318 319 int threadId() { return actualTC->threadId(); } 320 321 void setThreadId(int id) { return actualTC->setThreadId(id); } 322 323 int contextId() { return actualTC->contextId(); } 324 325 void setContextId(int id) { actualTC->setContextId(id); } 326 327 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 328 329 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 330 331 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 332 333 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 334 335 System *getSystemPtr() { return actualTC->getSystemPtr(); } 336 337 TheISA::Kernel::Statistics *getKernelStats() 338 { return actualTC->getKernelStats(); } 339 340 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 341 342 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 343 344 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 345 346 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 347 348 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 349 350 Status status() const { return actualTC->status(); } 351 352 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 353 354 /// Set the status to Active. Optional delay indicates number of 355 /// cycles to wait before beginning execution. 356 void activate(Cycles delay = Cycles(1)) 357 { actualTC->activate(delay); } 358 359 /// Set the status to Suspended. 360 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 361 362 /// Set the status to Halted. 363 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 364 365 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 366 367 void takeOverFrom(ThreadContext *oldContext) 368 { actualTC->takeOverFrom(oldContext); } 369 370 void regStats(const std::string &name) { actualTC->regStats(name); } 371 372 void serialize(std::ostream &os) { actualTC->serialize(os); } 373 void unserialize(Checkpoint *cp, const std::string §ion) 374 { actualTC->unserialize(cp, section); } 375 376 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 377 378 Tick readLastActivate() { return actualTC->readLastActivate(); } 379 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 380 381 void profileClear() { return actualTC->profileClear(); } 382 void profileSample() { return actualTC->profileSample(); } 383 384 // @todo: Do I need this? 385 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 386 387 void clearArchRegs() { actualTC->clearArchRegs(); } 388 389 // 390 // New accessors for new decoder. 391 // 392 uint64_t readIntReg(int reg_idx) 393 { return actualTC->readIntReg(reg_idx); } 394 395 FloatReg readFloatReg(int reg_idx) 396 { return actualTC->readFloatReg(reg_idx); } 397 398 FloatRegBits readFloatRegBits(int reg_idx) 399 { return actualTC->readFloatRegBits(reg_idx); } 400 401 void setIntReg(int reg_idx, uint64_t val) 402 { actualTC->setIntReg(reg_idx, val); } 403 404 void setFloatReg(int reg_idx, FloatReg val) 405 { actualTC->setFloatReg(reg_idx, val); } 406 407 void setFloatRegBits(int reg_idx, FloatRegBits val) 408 { actualTC->setFloatRegBits(reg_idx, val); } 409 410 TheISA::PCState pcState() { return actualTC->pcState(); } 411 412 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 413 414 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 415 416 Addr instAddr() { return actualTC->instAddr(); } 417 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 418 MicroPC microPC() { return actualTC->microPC(); } 419 420 bool readPredicate() { return actualTC->readPredicate(); } 421 422 void setPredicate(bool val) 423 { actualTC->setPredicate(val); } 424 425 MiscReg readMiscRegNoEffect(int misc_reg) 426 { return actualTC->readMiscRegNoEffect(misc_reg); } 427 428 MiscReg readMiscReg(int misc_reg) 429 { return actualTC->readMiscReg(misc_reg); } 430 431 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 432 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 433 434 void setMiscReg(int misc_reg, const MiscReg &val) 435 { return actualTC->setMiscReg(misc_reg, val); } 436 437 int flattenIntIndex(int reg) 438 { return actualTC->flattenIntIndex(reg); } 439 440 int flattenFloatIndex(int reg) 441 { return actualTC->flattenFloatIndex(reg); } 442 443 unsigned readStCondFailures() 444 { return actualTC->readStCondFailures(); } 445 446 void setStCondFailures(unsigned sc_failures) 447 { actualTC->setStCondFailures(sc_failures); } 448 449 // @todo: Fix this! 450 bool misspeculating() { return actualTC->misspeculating(); } 451 452 void syscall(int64_t callnum) 453 { actualTC->syscall(callnum); } 454 455 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 456 457 uint64_t readIntRegFlat(int idx) 458 { return actualTC->readIntRegFlat(idx); } 459 460 void setIntRegFlat(int idx, uint64_t val) 461 { actualTC->setIntRegFlat(idx, val); } 462 463 FloatReg readFloatRegFlat(int idx) 464 { return actualTC->readFloatRegFlat(idx); } 465 466 void setFloatRegFlat(int idx, FloatReg val) 467 { actualTC->setFloatRegFlat(idx, val); } 468 469 FloatRegBits readFloatRegBitsFlat(int idx) 470 { return actualTC->readFloatRegBitsFlat(idx); } 471 472 void setFloatRegBitsFlat(int idx, FloatRegBits val) 473 { actualTC->setFloatRegBitsFlat(idx, val); } 474}; 475 476#endif 477