thread_context.hh revision 8706:b1838faf3bcc
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include <iostream> 35#include <string> 36 37#include "arch/registers.hh" 38#include "arch/types.hh" 39#include "base/types.hh" 40#include "config/full_system.hh" 41#include "config/the_isa.hh" 42 43// @todo: Figure out a more architecture independent way to obtain the ITB and 44// DTB pointers. 45namespace TheISA 46{ 47 class TLB; 48} 49class BaseCPU; 50class Checkpoint; 51class Decoder; 52class EndQuiesceEvent; 53class SETranslatingPortProxy; 54class FSTranslatingPortProxy; 55class PortProxy; 56class Process; 57class System; 58namespace TheISA { 59 namespace Kernel { 60 class Statistics; 61 }; 62}; 63 64/** 65 * ThreadContext is the external interface to all thread state for 66 * anything outside of the CPU. It provides all accessor methods to 67 * state that might be needed by external objects, ranging from 68 * register values to things such as kernel stats. It is an abstract 69 * base class; the CPU can create its own ThreadContext by either 70 * deriving from it, or using the templated ProxyThreadContext. 71 * 72 * The ThreadContext is slightly different than the ExecContext. The 73 * ThreadContext provides access to an individual thread's state; an 74 * ExecContext provides ISA access to the CPU (meaning it is 75 * implicitly multithreaded on SMT systems). Additionally the 76 * ThreadState is an abstract class that exactly defines the 77 * interface; the ExecContext is a more implicit interface that must 78 * be implemented so that the ISA can access whatever state it needs. 79 */ 80class ThreadContext 81{ 82 protected: 83 typedef TheISA::MachInst MachInst; 84 typedef TheISA::IntReg IntReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 typedef TheISA::MiscReg MiscReg; 88 public: 89 90 enum Status 91 { 92 /// Running. Instructions should be executed only when 93 /// the context is in this state. 94 Active, 95 96 /// Temporarily inactive. Entered while waiting for 97 /// synchronization, etc. 98 Suspended, 99 100 /// Permanently shut down. Entered when target executes 101 /// m5exit pseudo-instruction. When all contexts enter 102 /// this state, the simulation will terminate. 103 Halted 104 }; 105 106 virtual ~ThreadContext() { }; 107 108 virtual BaseCPU *getCpuPtr() = 0; 109 110 virtual int cpuId() = 0; 111 112 virtual int threadId() = 0; 113 114 virtual void setThreadId(int id) = 0; 115 116 virtual int contextId() = 0; 117 118 virtual void setContextId(int id) = 0; 119 120 virtual TheISA::TLB *getITBPtr() = 0; 121 122 virtual TheISA::TLB *getDTBPtr() = 0; 123 124 virtual Decoder *getDecoderPtr() = 0; 125 126 virtual System *getSystemPtr() = 0; 127 128#if FULL_SYSTEM 129 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 130 131 virtual PortProxy* getPhysProxy() = 0; 132 133 virtual FSTranslatingPortProxy* getVirtProxy() = 0; 134 135 /** 136 * Initialise the physical and virtual port proxies and tie them to 137 * the data port of the CPU. 138 * 139 * tc ThreadContext for the virtual-to-physical translation 140 */ 141 virtual void initMemProxies(ThreadContext *tc) = 0; 142#else 143 virtual SETranslatingPortProxy *getMemProxy() = 0; 144 145 virtual Process *getProcessPtr() = 0; 146#endif 147 148 virtual Status status() const = 0; 149 150 virtual void setStatus(Status new_status) = 0; 151 152 /// Set the status to Active. Optional delay indicates number of 153 /// cycles to wait before beginning execution. 154 virtual void activate(int delay = 1) = 0; 155 156 /// Set the status to Suspended. 157 virtual void suspend(int delay = 0) = 0; 158 159 /// Set the status to Halted. 160 virtual void halt(int delay = 0) = 0; 161 162#if FULL_SYSTEM 163 virtual void dumpFuncProfile() = 0; 164#endif 165 166 virtual void takeOverFrom(ThreadContext *old_context) = 0; 167 168 virtual void regStats(const std::string &name) = 0; 169 170 virtual void serialize(std::ostream &os) = 0; 171 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 172 173#if FULL_SYSTEM 174 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 175 176 // Not necessarily the best location for these... 177 // Having an extra function just to read these is obnoxious 178 virtual Tick readLastActivate() = 0; 179 virtual Tick readLastSuspend() = 0; 180 181 virtual void profileClear() = 0; 182 virtual void profileSample() = 0; 183#endif 184 185 virtual void copyArchRegs(ThreadContext *tc) = 0; 186 187 virtual void clearArchRegs() = 0; 188 189 // 190 // New accessors for new decoder. 191 // 192 virtual uint64_t readIntReg(int reg_idx) = 0; 193 194 virtual FloatReg readFloatReg(int reg_idx) = 0; 195 196 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 197 198 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 199 200 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 201 202 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 203 204 virtual TheISA::PCState pcState() = 0; 205 206 virtual void pcState(const TheISA::PCState &val) = 0; 207 208 virtual Addr instAddr() = 0; 209 210 virtual Addr nextInstAddr() = 0; 211 212 virtual MicroPC microPC() = 0; 213 214 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 215 216 virtual MiscReg readMiscReg(int misc_reg) = 0; 217 218 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 219 220 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 221 222 virtual int flattenIntIndex(int reg) = 0; 223 virtual int flattenFloatIndex(int reg) = 0; 224 225 virtual uint64_t 226 readRegOtherThread(int misc_reg, ThreadID tid) 227 { 228 return 0; 229 } 230 231 virtual void 232 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 233 { 234 } 235 236 // Also not necessarily the best location for these two. Hopefully will go 237 // away once we decide upon where st cond failures goes. 238 virtual unsigned readStCondFailures() = 0; 239 240 virtual void setStCondFailures(unsigned sc_failures) = 0; 241 242 // Only really makes sense for old CPU model. Still could be useful though. 243 virtual bool misspeculating() = 0; 244 245#if !FULL_SYSTEM 246 // Same with st cond failures. 247 virtual Counter readFuncExeInst() = 0; 248 249 virtual void syscall(int64_t callnum) = 0; 250 251 // This function exits the thread context in the CPU and returns 252 // 1 if the CPU has no more active threads (meaning it's OK to exit); 253 // Used in syscall-emulation mode when a thread calls the exit syscall. 254 virtual int exit() { return 1; }; 255#endif 256 257 /** function to compare two thread contexts (for debugging) */ 258 static void compare(ThreadContext *one, ThreadContext *two); 259}; 260 261/** 262 * ProxyThreadContext class that provides a way to implement a 263 * ThreadContext without having to derive from it. ThreadContext is an 264 * abstract class, so anything that derives from it and uses its 265 * interface will pay the overhead of virtual function calls. This 266 * class is created to enable a user-defined Thread object to be used 267 * wherever ThreadContexts are used, without paying the overhead of 268 * virtual function calls when it is used by itself. See 269 * simple_thread.hh for an example of this. 270 */ 271template <class TC> 272class ProxyThreadContext : public ThreadContext 273{ 274 public: 275 ProxyThreadContext(TC *actual_tc) 276 { actualTC = actual_tc; } 277 278 private: 279 TC *actualTC; 280 281 public: 282 283 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 284 285 int cpuId() { return actualTC->cpuId(); } 286 287 int threadId() { return actualTC->threadId(); } 288 289 void setThreadId(int id) { return actualTC->setThreadId(id); } 290 291 int contextId() { return actualTC->contextId(); } 292 293 void setContextId(int id) { actualTC->setContextId(id); } 294 295 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 296 297 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 298 299 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 300 301 System *getSystemPtr() { return actualTC->getSystemPtr(); } 302 303#if FULL_SYSTEM 304 TheISA::Kernel::Statistics *getKernelStats() 305 { return actualTC->getKernelStats(); } 306 307 PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 308 309 FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } 310 311 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 312#else 313 SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } 314 315 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 316#endif 317 318 Status status() const { return actualTC->status(); } 319 320 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 321 322 /// Set the status to Active. Optional delay indicates number of 323 /// cycles to wait before beginning execution. 324 void activate(int delay = 1) { actualTC->activate(delay); } 325 326 /// Set the status to Suspended. 327 void suspend(int delay = 0) { actualTC->suspend(); } 328 329 /// Set the status to Halted. 330 void halt(int delay = 0) { actualTC->halt(); } 331 332#if FULL_SYSTEM 333 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 334#endif 335 336 void takeOverFrom(ThreadContext *oldContext) 337 { actualTC->takeOverFrom(oldContext); } 338 339 void regStats(const std::string &name) { actualTC->regStats(name); } 340 341 void serialize(std::ostream &os) { actualTC->serialize(os); } 342 void unserialize(Checkpoint *cp, const std::string §ion) 343 { actualTC->unserialize(cp, section); } 344 345#if FULL_SYSTEM 346 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 347 348 Tick readLastActivate() { return actualTC->readLastActivate(); } 349 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 350 351 void profileClear() { return actualTC->profileClear(); } 352 void profileSample() { return actualTC->profileSample(); } 353#endif 354 355 // @todo: Do I need this? 356 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 357 358 void clearArchRegs() { actualTC->clearArchRegs(); } 359 360 // 361 // New accessors for new decoder. 362 // 363 uint64_t readIntReg(int reg_idx) 364 { return actualTC->readIntReg(reg_idx); } 365 366 FloatReg readFloatReg(int reg_idx) 367 { return actualTC->readFloatReg(reg_idx); } 368 369 FloatRegBits readFloatRegBits(int reg_idx) 370 { return actualTC->readFloatRegBits(reg_idx); } 371 372 void setIntReg(int reg_idx, uint64_t val) 373 { actualTC->setIntReg(reg_idx, val); } 374 375 void setFloatReg(int reg_idx, FloatReg val) 376 { actualTC->setFloatReg(reg_idx, val); } 377 378 void setFloatRegBits(int reg_idx, FloatRegBits val) 379 { actualTC->setFloatRegBits(reg_idx, val); } 380 381 TheISA::PCState pcState() { return actualTC->pcState(); } 382 383 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 384 385 Addr instAddr() { return actualTC->instAddr(); } 386 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 387 MicroPC microPC() { return actualTC->microPC(); } 388 389 bool readPredicate() { return actualTC->readPredicate(); } 390 391 void setPredicate(bool val) 392 { actualTC->setPredicate(val); } 393 394 MiscReg readMiscRegNoEffect(int misc_reg) 395 { return actualTC->readMiscRegNoEffect(misc_reg); } 396 397 MiscReg readMiscReg(int misc_reg) 398 { return actualTC->readMiscReg(misc_reg); } 399 400 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 401 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 402 403 void setMiscReg(int misc_reg, const MiscReg &val) 404 { return actualTC->setMiscReg(misc_reg, val); } 405 406 int flattenIntIndex(int reg) 407 { return actualTC->flattenIntIndex(reg); } 408 409 int flattenFloatIndex(int reg) 410 { return actualTC->flattenFloatIndex(reg); } 411 412 unsigned readStCondFailures() 413 { return actualTC->readStCondFailures(); } 414 415 void setStCondFailures(unsigned sc_failures) 416 { actualTC->setStCondFailures(sc_failures); } 417 418 // @todo: Fix this! 419 bool misspeculating() { return actualTC->misspeculating(); } 420 421#if !FULL_SYSTEM 422 void syscall(int64_t callnum) 423 { actualTC->syscall(callnum); } 424 425 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 426#endif 427}; 428 429#endif 430