thread_context.hh revision 7679:f26cc2c68b48
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "arch/registers.hh" 35#include "arch/types.hh" 36#include "base/types.hh" 37#include "config/full_system.hh" 38#include "config/the_isa.hh" 39#include "sim/serialize.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43namespace TheISA 44{ 45 class TLB; 46} 47class BaseCPU; 48class EndQuiesceEvent; 49class Event; 50class TranslatingPort; 51class FunctionalPort; 52class VirtualPort; 53class Process; 54class System; 55namespace TheISA { 56 namespace Kernel { 57 class Statistics; 58 }; 59}; 60 61/** 62 * ThreadContext is the external interface to all thread state for 63 * anything outside of the CPU. It provides all accessor methods to 64 * state that might be needed by external objects, ranging from 65 * register values to things such as kernel stats. It is an abstract 66 * base class; the CPU can create its own ThreadContext by either 67 * deriving from it, or using the templated ProxyThreadContext. 68 * 69 * The ThreadContext is slightly different than the ExecContext. The 70 * ThreadContext provides access to an individual thread's state; an 71 * ExecContext provides ISA access to the CPU (meaning it is 72 * implicitly multithreaded on SMT systems). Additionally the 73 * ThreadState is an abstract class that exactly defines the 74 * interface; the ExecContext is a more implicit interface that must 75 * be implemented so that the ISA can access whatever state it needs. 76 */ 77class ThreadContext 78{ 79 protected: 80 typedef TheISA::MachInst MachInst; 81 typedef TheISA::IntReg IntReg; 82 typedef TheISA::FloatReg FloatReg; 83 typedef TheISA::FloatRegBits FloatRegBits; 84 typedef TheISA::MiscReg MiscReg; 85 public: 86 87 enum Status 88 { 89 /// Running. Instructions should be executed only when 90 /// the context is in this state. 91 Active, 92 93 /// Temporarily inactive. Entered while waiting for 94 /// synchronization, etc. 95 Suspended, 96 97 /// Permanently shut down. Entered when target executes 98 /// m5exit pseudo-instruction. When all contexts enter 99 /// this state, the simulation will terminate. 100 Halted 101 }; 102 103 virtual ~ThreadContext() { }; 104 105 virtual BaseCPU *getCpuPtr() = 0; 106 107 virtual int cpuId() = 0; 108 109 virtual int threadId() = 0; 110 111 virtual void setThreadId(int id) = 0; 112 113 virtual int contextId() = 0; 114 115 virtual void setContextId(int id) = 0; 116 117 virtual TheISA::TLB *getITBPtr() = 0; 118 119 virtual TheISA::TLB *getDTBPtr() = 0; 120 121 virtual System *getSystemPtr() = 0; 122 123#if FULL_SYSTEM 124 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 125 126 virtual FunctionalPort *getPhysPort() = 0; 127 128 virtual VirtualPort *getVirtPort() = 0; 129 130 virtual void connectMemPorts(ThreadContext *tc) = 0; 131#else 132 virtual TranslatingPort *getMemPort() = 0; 133 134 virtual Process *getProcessPtr() = 0; 135#endif 136 137 virtual Status status() const = 0; 138 139 virtual void setStatus(Status new_status) = 0; 140 141 /// Set the status to Active. Optional delay indicates number of 142 /// cycles to wait before beginning execution. 143 virtual void activate(int delay = 1) = 0; 144 145 /// Set the status to Suspended. 146 virtual void suspend(int delay = 0) = 0; 147 148 /// Set the status to Halted. 149 virtual void halt(int delay = 0) = 0; 150 151#if FULL_SYSTEM 152 virtual void dumpFuncProfile() = 0; 153#endif 154 155 virtual void takeOverFrom(ThreadContext *old_context) = 0; 156 157 virtual void regStats(const std::string &name) = 0; 158 159 virtual void serialize(std::ostream &os) = 0; 160 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 161 162#if FULL_SYSTEM 163 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 164 165 // Not necessarily the best location for these... 166 // Having an extra function just to read these is obnoxious 167 virtual Tick readLastActivate() = 0; 168 virtual Tick readLastSuspend() = 0; 169 170 virtual void profileClear() = 0; 171 virtual void profileSample() = 0; 172#endif 173 174 virtual void copyArchRegs(ThreadContext *tc) = 0; 175 176 virtual void clearArchRegs() = 0; 177 178 // 179 // New accessors for new decoder. 180 // 181 virtual uint64_t readIntReg(int reg_idx) = 0; 182 183 virtual FloatReg readFloatReg(int reg_idx) = 0; 184 185 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 186 187 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 188 189 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 190 191 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 192 193 virtual uint64_t readPC() = 0; 194 195 virtual void setPC(uint64_t val) = 0; 196 197 virtual uint64_t readNextPC() = 0; 198 199 virtual void setNextPC(uint64_t val) = 0; 200 201 virtual uint64_t readNextNPC() = 0; 202 203 virtual void setNextNPC(uint64_t val) = 0; 204 205 virtual uint64_t readMicroPC() = 0; 206 207 virtual void setMicroPC(uint64_t val) = 0; 208 209 virtual uint64_t readNextMicroPC() = 0; 210 211 virtual void setNextMicroPC(uint64_t val) = 0; 212 213 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 214 215 virtual MiscReg readMiscReg(int misc_reg) = 0; 216 217 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 218 219 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 220 221 virtual int flattenIntIndex(int reg) = 0; 222 virtual int flattenFloatIndex(int reg) = 0; 223 224 virtual uint64_t 225 readRegOtherThread(int misc_reg, ThreadID tid) 226 { 227 return 0; 228 } 229 230 virtual void 231 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 232 { 233 } 234 235 // Also not necessarily the best location for these two. Hopefully will go 236 // away once we decide upon where st cond failures goes. 237 virtual unsigned readStCondFailures() = 0; 238 239 virtual void setStCondFailures(unsigned sc_failures) = 0; 240 241 // Only really makes sense for old CPU model. Still could be useful though. 242 virtual bool misspeculating() = 0; 243 244#if !FULL_SYSTEM 245 // Same with st cond failures. 246 virtual Counter readFuncExeInst() = 0; 247 248 virtual void syscall(int64_t callnum) = 0; 249 250 // This function exits the thread context in the CPU and returns 251 // 1 if the CPU has no more active threads (meaning it's OK to exit); 252 // Used in syscall-emulation mode when a thread calls the exit syscall. 253 virtual int exit() { return 1; }; 254#endif 255 256 /** function to compare two thread contexts (for debugging) */ 257 static void compare(ThreadContext *one, ThreadContext *two); 258}; 259 260/** 261 * ProxyThreadContext class that provides a way to implement a 262 * ThreadContext without having to derive from it. ThreadContext is an 263 * abstract class, so anything that derives from it and uses its 264 * interface will pay the overhead of virtual function calls. This 265 * class is created to enable a user-defined Thread object to be used 266 * wherever ThreadContexts are used, without paying the overhead of 267 * virtual function calls when it is used by itself. See 268 * simple_thread.hh for an example of this. 269 */ 270template <class TC> 271class ProxyThreadContext : public ThreadContext 272{ 273 public: 274 ProxyThreadContext(TC *actual_tc) 275 { actualTC = actual_tc; } 276 277 private: 278 TC *actualTC; 279 280 public: 281 282 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 283 284 int cpuId() { return actualTC->cpuId(); } 285 286 int threadId() { return actualTC->threadId(); } 287 288 void setThreadId(int id) { return actualTC->setThreadId(id); } 289 290 int contextId() { return actualTC->contextId(); } 291 292 void setContextId(int id) { actualTC->setContextId(id); } 293 294 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 295 296 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 297 298 System *getSystemPtr() { return actualTC->getSystemPtr(); } 299 300#if FULL_SYSTEM 301 TheISA::Kernel::Statistics *getKernelStats() 302 { return actualTC->getKernelStats(); } 303 304 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 305 306 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 307 308 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 309#else 310 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 311 312 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 313#endif 314 315 Status status() const { return actualTC->status(); } 316 317 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 318 319 /// Set the status to Active. Optional delay indicates number of 320 /// cycles to wait before beginning execution. 321 void activate(int delay = 1) { actualTC->activate(delay); } 322 323 /// Set the status to Suspended. 324 void suspend(int delay = 0) { actualTC->suspend(); } 325 326 /// Set the status to Halted. 327 void halt(int delay = 0) { actualTC->halt(); } 328 329#if FULL_SYSTEM 330 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 331#endif 332 333 void takeOverFrom(ThreadContext *oldContext) 334 { actualTC->takeOverFrom(oldContext); } 335 336 void regStats(const std::string &name) { actualTC->regStats(name); } 337 338 void serialize(std::ostream &os) { actualTC->serialize(os); } 339 void unserialize(Checkpoint *cp, const std::string §ion) 340 { actualTC->unserialize(cp, section); } 341 342#if FULL_SYSTEM 343 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 344 345 Tick readLastActivate() { return actualTC->readLastActivate(); } 346 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 347 348 void profileClear() { return actualTC->profileClear(); } 349 void profileSample() { return actualTC->profileSample(); } 350#endif 351 352 // @todo: Do I need this? 353 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 354 355 void clearArchRegs() { actualTC->clearArchRegs(); } 356 357 // 358 // New accessors for new decoder. 359 // 360 uint64_t readIntReg(int reg_idx) 361 { return actualTC->readIntReg(reg_idx); } 362 363 FloatReg readFloatReg(int reg_idx) 364 { return actualTC->readFloatReg(reg_idx); } 365 366 FloatRegBits readFloatRegBits(int reg_idx) 367 { return actualTC->readFloatRegBits(reg_idx); } 368 369 void setIntReg(int reg_idx, uint64_t val) 370 { actualTC->setIntReg(reg_idx, val); } 371 372 void setFloatReg(int reg_idx, FloatReg val) 373 { actualTC->setFloatReg(reg_idx, val); } 374 375 void setFloatRegBits(int reg_idx, FloatRegBits val) 376 { actualTC->setFloatRegBits(reg_idx, val); } 377 378 uint64_t readPC() { return actualTC->readPC(); } 379 380 void setPC(uint64_t val) { actualTC->setPC(val); } 381 382 uint64_t readNextPC() { return actualTC->readNextPC(); } 383 384 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 385 386 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 387 388 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 389 390 uint64_t readMicroPC() { return actualTC->readMicroPC(); } 391 392 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 393 394 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 395 396 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 397 398 bool readPredicate() { return actualTC->readPredicate(); } 399 400 void setPredicate(bool val) 401 { actualTC->setPredicate(val); } 402 403 MiscReg readMiscRegNoEffect(int misc_reg) 404 { return actualTC->readMiscRegNoEffect(misc_reg); } 405 406 MiscReg readMiscReg(int misc_reg) 407 { return actualTC->readMiscReg(misc_reg); } 408 409 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 410 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 411 412 void setMiscReg(int misc_reg, const MiscReg &val) 413 { return actualTC->setMiscReg(misc_reg, val); } 414 415 int flattenIntIndex(int reg) 416 { return actualTC->flattenIntIndex(reg); } 417 418 int flattenFloatIndex(int reg) 419 { return actualTC->flattenFloatIndex(reg); } 420 421 unsigned readStCondFailures() 422 { return actualTC->readStCondFailures(); } 423 424 void setStCondFailures(unsigned sc_failures) 425 { actualTC->setStCondFailures(sc_failures); } 426 427 // @todo: Fix this! 428 bool misspeculating() { return actualTC->misspeculating(); } 429 430#if !FULL_SYSTEM 431 void syscall(int64_t callnum) 432 { actualTC->syscall(callnum); } 433 434 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 435#endif 436}; 437 438#endif 439