thread_context.hh revision 6313:95f69a436c82
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "arch/regfile.hh" 35#include "arch/types.hh" 36#include "base/types.hh" 37#include "config/full_system.hh" 38#include "mem/request.hh" 39#include "sim/byteswap.hh" 40#include "sim/faults.hh" 41#include "sim/serialize.hh" 42 43// @todo: Figure out a more architecture independent way to obtain the ITB and 44// DTB pointers. 45namespace TheISA 46{ 47 class TLB; 48} 49class BaseCPU; 50class EndQuiesceEvent; 51class Event; 52class TranslatingPort; 53class FunctionalPort; 54class VirtualPort; 55class Process; 56class System; 57namespace TheISA { 58 namespace Kernel { 59 class Statistics; 60 }; 61}; 62 63/** 64 * ThreadContext is the external interface to all thread state for 65 * anything outside of the CPU. It provides all accessor methods to 66 * state that might be needed by external objects, ranging from 67 * register values to things such as kernel stats. It is an abstract 68 * base class; the CPU can create its own ThreadContext by either 69 * deriving from it, or using the templated ProxyThreadContext. 70 * 71 * The ThreadContext is slightly different than the ExecContext. The 72 * ThreadContext provides access to an individual thread's state; an 73 * ExecContext provides ISA access to the CPU (meaning it is 74 * implicitly multithreaded on SMT systems). Additionally the 75 * ThreadState is an abstract class that exactly defines the 76 * interface; the ExecContext is a more implicit interface that must 77 * be implemented so that the ISA can access whatever state it needs. 78 */ 79class ThreadContext 80{ 81 protected: 82 typedef TheISA::RegFile RegFile; 83 typedef TheISA::MachInst MachInst; 84 typedef TheISA::IntReg IntReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 typedef TheISA::MiscReg MiscReg; 88 public: 89 90 enum Status 91 { 92 /// Running. Instructions should be executed only when 93 /// the context is in this state. 94 Active, 95 96 /// Temporarily inactive. Entered while waiting for 97 /// synchronization, etc. 98 Suspended, 99 100 /// Permanently shut down. Entered when target executes 101 /// m5exit pseudo-instruction. When all contexts enter 102 /// this state, the simulation will terminate. 103 Halted 104 }; 105 106 virtual ~ThreadContext() { }; 107 108 virtual BaseCPU *getCpuPtr() = 0; 109 110 virtual int cpuId() = 0; 111 112 virtual int threadId() = 0; 113 114 virtual void setThreadId(int id) = 0; 115 116 virtual int contextId() = 0; 117 118 virtual void setContextId(int id) = 0; 119 120 virtual TheISA::TLB *getITBPtr() = 0; 121 122 virtual TheISA::TLB *getDTBPtr() = 0; 123 124 virtual System *getSystemPtr() = 0; 125 126#if FULL_SYSTEM 127 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 128 129 virtual FunctionalPort *getPhysPort() = 0; 130 131 virtual VirtualPort *getVirtPort() = 0; 132 133 virtual void connectMemPorts(ThreadContext *tc) = 0; 134#else 135 virtual TranslatingPort *getMemPort() = 0; 136 137 virtual Process *getProcessPtr() = 0; 138#endif 139 140 virtual Status status() const = 0; 141 142 virtual void setStatus(Status new_status) = 0; 143 144 /// Set the status to Active. Optional delay indicates number of 145 /// cycles to wait before beginning execution. 146 virtual void activate(int delay = 1) = 0; 147 148 /// Set the status to Suspended. 149 virtual void suspend(int delay = 0) = 0; 150 151 /// Set the status to Halted. 152 virtual void halt(int delay = 0) = 0; 153 154#if FULL_SYSTEM 155 virtual void dumpFuncProfile() = 0; 156#endif 157 158 virtual void takeOverFrom(ThreadContext *old_context) = 0; 159 160 virtual void regStats(const std::string &name) = 0; 161 162 virtual void serialize(std::ostream &os) = 0; 163 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 164 165#if FULL_SYSTEM 166 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 167 168 // Not necessarily the best location for these... 169 // Having an extra function just to read these is obnoxious 170 virtual Tick readLastActivate() = 0; 171 virtual Tick readLastSuspend() = 0; 172 173 virtual void profileClear() = 0; 174 virtual void profileSample() = 0; 175#endif 176 177 // Also somewhat obnoxious. Really only used for the TLB fault. 178 // However, may be quite useful in SPARC. 179 virtual TheISA::MachInst getInst() = 0; 180 181 virtual void copyArchRegs(ThreadContext *tc) = 0; 182 183 virtual void clearArchRegs() = 0; 184 185 // 186 // New accessors for new decoder. 187 // 188 virtual uint64_t readIntReg(int reg_idx) = 0; 189 190 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 191 192 virtual FloatReg readFloatReg(int reg_idx) = 0; 193 194 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 195 196 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 197 198 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 199 200 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 201 202 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 203 204 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 205 206 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 207 208 virtual uint64_t readPC() = 0; 209 210 virtual void setPC(uint64_t val) = 0; 211 212 virtual uint64_t readNextPC() = 0; 213 214 virtual void setNextPC(uint64_t val) = 0; 215 216 virtual uint64_t readNextNPC() = 0; 217 218 virtual void setNextNPC(uint64_t val) = 0; 219 220 virtual uint64_t readMicroPC() = 0; 221 222 virtual void setMicroPC(uint64_t val) = 0; 223 224 virtual uint64_t readNextMicroPC() = 0; 225 226 virtual void setNextMicroPC(uint64_t val) = 0; 227 228 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 229 230 virtual MiscReg readMiscReg(int misc_reg) = 0; 231 232 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 233 234 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 235 236 virtual int flattenIntIndex(int reg) = 0; 237 virtual int flattenFloatIndex(int reg) = 0; 238 239 virtual uint64_t 240 readRegOtherThread(int misc_reg, ThreadID tid) 241 { 242 return 0; 243 } 244 245 virtual void 246 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 247 { 248 } 249 250 // Also not necessarily the best location for these two. Hopefully will go 251 // away once we decide upon where st cond failures goes. 252 virtual unsigned readStCondFailures() = 0; 253 254 virtual void setStCondFailures(unsigned sc_failures) = 0; 255 256 // Only really makes sense for old CPU model. Still could be useful though. 257 virtual bool misspeculating() = 0; 258 259#if !FULL_SYSTEM 260 // Same with st cond failures. 261 virtual Counter readFuncExeInst() = 0; 262 263 virtual void syscall(int64_t callnum) = 0; 264 265 // This function exits the thread context in the CPU and returns 266 // 1 if the CPU has no more active threads (meaning it's OK to exit); 267 // Used in syscall-emulation mode when a thread calls the exit syscall. 268 virtual int exit() { return 1; }; 269#endif 270 271 /** function to compare two thread contexts (for debugging) */ 272 static void compare(ThreadContext *one, ThreadContext *two); 273}; 274 275/** 276 * ProxyThreadContext class that provides a way to implement a 277 * ThreadContext without having to derive from it. ThreadContext is an 278 * abstract class, so anything that derives from it and uses its 279 * interface will pay the overhead of virtual function calls. This 280 * class is created to enable a user-defined Thread object to be used 281 * wherever ThreadContexts are used, without paying the overhead of 282 * virtual function calls when it is used by itself. See 283 * simple_thread.hh for an example of this. 284 */ 285template <class TC> 286class ProxyThreadContext : public ThreadContext 287{ 288 public: 289 ProxyThreadContext(TC *actual_tc) 290 { actualTC = actual_tc; } 291 292 private: 293 TC *actualTC; 294 295 public: 296 297 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 298 299 int cpuId() { return actualTC->cpuId(); } 300 301 int threadId() { return actualTC->threadId(); } 302 303 void setThreadId(int id) { return actualTC->setThreadId(id); } 304 305 int contextId() { return actualTC->contextId(); } 306 307 void setContextId(int id) { actualTC->setContextId(id); } 308 309 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 310 311 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 312 313 System *getSystemPtr() { return actualTC->getSystemPtr(); } 314 315#if FULL_SYSTEM 316 TheISA::Kernel::Statistics *getKernelStats() 317 { return actualTC->getKernelStats(); } 318 319 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 320 321 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 322 323 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 324#else 325 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 326 327 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 328#endif 329 330 Status status() const { return actualTC->status(); } 331 332 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 333 334 /// Set the status to Active. Optional delay indicates number of 335 /// cycles to wait before beginning execution. 336 void activate(int delay = 1) { actualTC->activate(delay); } 337 338 /// Set the status to Suspended. 339 void suspend(int delay = 0) { actualTC->suspend(); } 340 341 /// Set the status to Halted. 342 void halt(int delay = 0) { actualTC->halt(); } 343 344#if FULL_SYSTEM 345 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 346#endif 347 348 void takeOverFrom(ThreadContext *oldContext) 349 { actualTC->takeOverFrom(oldContext); } 350 351 void regStats(const std::string &name) { actualTC->regStats(name); } 352 353 void serialize(std::ostream &os) { actualTC->serialize(os); } 354 void unserialize(Checkpoint *cp, const std::string §ion) 355 { actualTC->unserialize(cp, section); } 356 357#if FULL_SYSTEM 358 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 359 360 Tick readLastActivate() { return actualTC->readLastActivate(); } 361 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 362 363 void profileClear() { return actualTC->profileClear(); } 364 void profileSample() { return actualTC->profileSample(); } 365#endif 366 // @todo: Do I need this? 367 MachInst getInst() { return actualTC->getInst(); } 368 369 // @todo: Do I need this? 370 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 371 372 void clearArchRegs() { actualTC->clearArchRegs(); } 373 374 // 375 // New accessors for new decoder. 376 // 377 uint64_t readIntReg(int reg_idx) 378 { return actualTC->readIntReg(reg_idx); } 379 380 FloatReg readFloatReg(int reg_idx, int width) 381 { return actualTC->readFloatReg(reg_idx, width); } 382 383 FloatReg readFloatReg(int reg_idx) 384 { return actualTC->readFloatReg(reg_idx); } 385 386 FloatRegBits readFloatRegBits(int reg_idx, int width) 387 { return actualTC->readFloatRegBits(reg_idx, width); } 388 389 FloatRegBits readFloatRegBits(int reg_idx) 390 { return actualTC->readFloatRegBits(reg_idx); } 391 392 void setIntReg(int reg_idx, uint64_t val) 393 { actualTC->setIntReg(reg_idx, val); } 394 395 void setFloatReg(int reg_idx, FloatReg val, int width) 396 { actualTC->setFloatReg(reg_idx, val, width); } 397 398 void setFloatReg(int reg_idx, FloatReg val) 399 { actualTC->setFloatReg(reg_idx, val); } 400 401 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 402 { actualTC->setFloatRegBits(reg_idx, val, width); } 403 404 void setFloatRegBits(int reg_idx, FloatRegBits val) 405 { actualTC->setFloatRegBits(reg_idx, val); } 406 407 uint64_t readPC() { return actualTC->readPC(); } 408 409 void setPC(uint64_t val) { actualTC->setPC(val); } 410 411 uint64_t readNextPC() { return actualTC->readNextPC(); } 412 413 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 414 415 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 416 417 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 418 419 uint64_t readMicroPC() { return actualTC->readMicroPC(); } 420 421 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 422 423 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 424 425 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 426 427 MiscReg readMiscRegNoEffect(int misc_reg) 428 { return actualTC->readMiscRegNoEffect(misc_reg); } 429 430 MiscReg readMiscReg(int misc_reg) 431 { return actualTC->readMiscReg(misc_reg); } 432 433 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 434 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 435 436 void setMiscReg(int misc_reg, const MiscReg &val) 437 { return actualTC->setMiscReg(misc_reg, val); } 438 439 int flattenIntIndex(int reg) 440 { return actualTC->flattenIntIndex(reg); } 441 442 int flattenFloatIndex(int reg) 443 { return actualTC->flattenFloatIndex(reg); } 444 445 unsigned readStCondFailures() 446 { return actualTC->readStCondFailures(); } 447 448 void setStCondFailures(unsigned sc_failures) 449 { actualTC->setStCondFailures(sc_failures); } 450 451 // @todo: Fix this! 452 bool misspeculating() { return actualTC->misspeculating(); } 453 454#if !FULL_SYSTEM 455 void syscall(int64_t callnum) 456 { actualTC->syscall(callnum); } 457 458 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 459#endif 460}; 461 462#endif 463