thread_context.hh revision 6214:1ec0ec8933ae
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "arch/regfile.hh" 35#include "arch/types.hh" 36#include "config/full_system.hh" 37#include "mem/request.hh" 38#include "sim/faults.hh" 39#include "base/types.hh" 40#include "sim/serialize.hh" 41#include "sim/byteswap.hh" 42 43// @todo: Figure out a more architecture independent way to obtain the ITB and 44// DTB pointers. 45namespace TheISA 46{ 47 class TLB; 48} 49class BaseCPU; 50class EndQuiesceEvent; 51class Event; 52class TranslatingPort; 53class FunctionalPort; 54class VirtualPort; 55class Process; 56class System; 57namespace TheISA { 58 namespace Kernel { 59 class Statistics; 60 }; 61}; 62 63/** 64 * ThreadContext is the external interface to all thread state for 65 * anything outside of the CPU. It provides all accessor methods to 66 * state that might be needed by external objects, ranging from 67 * register values to things such as kernel stats. It is an abstract 68 * base class; the CPU can create its own ThreadContext by either 69 * deriving from it, or using the templated ProxyThreadContext. 70 * 71 * The ThreadContext is slightly different than the ExecContext. The 72 * ThreadContext provides access to an individual thread's state; an 73 * ExecContext provides ISA access to the CPU (meaning it is 74 * implicitly multithreaded on SMT systems). Additionally the 75 * ThreadState is an abstract class that exactly defines the 76 * interface; the ExecContext is a more implicit interface that must 77 * be implemented so that the ISA can access whatever state it needs. 78 */ 79class ThreadContext 80{ 81 protected: 82 typedef TheISA::RegFile RegFile; 83 typedef TheISA::MachInst MachInst; 84 typedef TheISA::IntReg IntReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 typedef TheISA::MiscRegFile MiscRegFile; 88 typedef TheISA::MiscReg MiscReg; 89 public: 90 91 enum Status 92 { 93 /// Running. Instructions should be executed only when 94 /// the context is in this state. 95 Active, 96 97 /// Temporarily inactive. Entered while waiting for 98 /// synchronization, etc. 99 Suspended, 100 101 /// Permanently shut down. Entered when target executes 102 /// m5exit pseudo-instruction. When all contexts enter 103 /// this state, the simulation will terminate. 104 Halted 105 }; 106 107 virtual ~ThreadContext() { }; 108 109 virtual BaseCPU *getCpuPtr() = 0; 110 111 virtual int cpuId() = 0; 112 113 virtual int threadId() = 0; 114 115 virtual void setThreadId(int id) = 0; 116 117 virtual int contextId() = 0; 118 119 virtual void setContextId(int id) = 0; 120 121 virtual TheISA::TLB *getITBPtr() = 0; 122 123 virtual TheISA::TLB *getDTBPtr() = 0; 124 125 virtual System *getSystemPtr() = 0; 126 127#if FULL_SYSTEM 128 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 129 130 virtual FunctionalPort *getPhysPort() = 0; 131 132 virtual VirtualPort *getVirtPort() = 0; 133 134 virtual void connectMemPorts(ThreadContext *tc) = 0; 135#else 136 virtual TranslatingPort *getMemPort() = 0; 137 138 virtual Process *getProcessPtr() = 0; 139#endif 140 141 virtual Status status() const = 0; 142 143 virtual void setStatus(Status new_status) = 0; 144 145 /// Set the status to Active. Optional delay indicates number of 146 /// cycles to wait before beginning execution. 147 virtual void activate(int delay = 1) = 0; 148 149 /// Set the status to Suspended. 150 virtual void suspend(int delay = 0) = 0; 151 152 /// Set the status to Halted. 153 virtual void halt(int delay = 0) = 0; 154 155#if FULL_SYSTEM 156 virtual void dumpFuncProfile() = 0; 157#endif 158 159 virtual void takeOverFrom(ThreadContext *old_context) = 0; 160 161 virtual void regStats(const std::string &name) = 0; 162 163 virtual void serialize(std::ostream &os) = 0; 164 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 165 166#if FULL_SYSTEM 167 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 168 169 // Not necessarily the best location for these... 170 // Having an extra function just to read these is obnoxious 171 virtual Tick readLastActivate() = 0; 172 virtual Tick readLastSuspend() = 0; 173 174 virtual void profileClear() = 0; 175 virtual void profileSample() = 0; 176#endif 177 178 // Also somewhat obnoxious. Really only used for the TLB fault. 179 // However, may be quite useful in SPARC. 180 virtual TheISA::MachInst getInst() = 0; 181 182 virtual void copyArchRegs(ThreadContext *tc) = 0; 183 184 virtual void clearArchRegs() = 0; 185 186 // 187 // New accessors for new decoder. 188 // 189 virtual uint64_t readIntReg(int reg_idx) = 0; 190 191 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 192 193 virtual FloatReg readFloatReg(int reg_idx) = 0; 194 195 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 196 197 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 198 199 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 200 201 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 202 203 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 204 205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 206 207 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 208 209 virtual uint64_t readPC() = 0; 210 211 virtual void setPC(uint64_t val) = 0; 212 213 virtual uint64_t readNextPC() = 0; 214 215 virtual void setNextPC(uint64_t val) = 0; 216 217 virtual uint64_t readNextNPC() = 0; 218 219 virtual void setNextNPC(uint64_t val) = 0; 220 221 virtual uint64_t readMicroPC() = 0; 222 223 virtual void setMicroPC(uint64_t val) = 0; 224 225 virtual uint64_t readNextMicroPC() = 0; 226 227 virtual void setNextMicroPC(uint64_t val) = 0; 228 229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 230 231 virtual MiscReg readMiscReg(int misc_reg) = 0; 232 233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 234 235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 236 237 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } 238 239 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; 240 241 // Also not necessarily the best location for these two. Hopefully will go 242 // away once we decide upon where st cond failures goes. 243 virtual unsigned readStCondFailures() = 0; 244 245 virtual void setStCondFailures(unsigned sc_failures) = 0; 246 247 // Only really makes sense for old CPU model. Still could be useful though. 248 virtual bool misspeculating() = 0; 249 250#if !FULL_SYSTEM 251 // Same with st cond failures. 252 virtual Counter readFuncExeInst() = 0; 253 254 virtual void syscall(int64_t callnum) = 0; 255 256 // This function exits the thread context in the CPU and returns 257 // 1 if the CPU has no more active threads (meaning it's OK to exit); 258 // Used in syscall-emulation mode when a thread calls the exit syscall. 259 virtual int exit() { return 1; }; 260#endif 261 262 /** function to compare two thread contexts (for debugging) */ 263 static void compare(ThreadContext *one, ThreadContext *two); 264}; 265 266/** 267 * ProxyThreadContext class that provides a way to implement a 268 * ThreadContext without having to derive from it. ThreadContext is an 269 * abstract class, so anything that derives from it and uses its 270 * interface will pay the overhead of virtual function calls. This 271 * class is created to enable a user-defined Thread object to be used 272 * wherever ThreadContexts are used, without paying the overhead of 273 * virtual function calls when it is used by itself. See 274 * simple_thread.hh for an example of this. 275 */ 276template <class TC> 277class ProxyThreadContext : public ThreadContext 278{ 279 public: 280 ProxyThreadContext(TC *actual_tc) 281 { actualTC = actual_tc; } 282 283 private: 284 TC *actualTC; 285 286 public: 287 288 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 289 290 int cpuId() { return actualTC->cpuId(); } 291 292 int threadId() { return actualTC->threadId(); } 293 294 void setThreadId(int id) { return actualTC->setThreadId(id); } 295 296 int contextId() { return actualTC->contextId(); } 297 298 void setContextId(int id) { actualTC->setContextId(id); } 299 300 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 301 302 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 303 304 System *getSystemPtr() { return actualTC->getSystemPtr(); } 305 306#if FULL_SYSTEM 307 TheISA::Kernel::Statistics *getKernelStats() 308 { return actualTC->getKernelStats(); } 309 310 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 311 312 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 313 314 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 315#else 316 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 317 318 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 319#endif 320 321 Status status() const { return actualTC->status(); } 322 323 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 324 325 /// Set the status to Active. Optional delay indicates number of 326 /// cycles to wait before beginning execution. 327 void activate(int delay = 1) { actualTC->activate(delay); } 328 329 /// Set the status to Suspended. 330 void suspend(int delay = 0) { actualTC->suspend(); } 331 332 /// Set the status to Halted. 333 void halt(int delay = 0) { actualTC->halt(); } 334 335#if FULL_SYSTEM 336 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 337#endif 338 339 void takeOverFrom(ThreadContext *oldContext) 340 { actualTC->takeOverFrom(oldContext); } 341 342 void regStats(const std::string &name) { actualTC->regStats(name); } 343 344 void serialize(std::ostream &os) { actualTC->serialize(os); } 345 void unserialize(Checkpoint *cp, const std::string §ion) 346 { actualTC->unserialize(cp, section); } 347 348#if FULL_SYSTEM 349 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 350 351 Tick readLastActivate() { return actualTC->readLastActivate(); } 352 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 353 354 void profileClear() { return actualTC->profileClear(); } 355 void profileSample() { return actualTC->profileSample(); } 356#endif 357 // @todo: Do I need this? 358 MachInst getInst() { return actualTC->getInst(); } 359 360 // @todo: Do I need this? 361 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 362 363 void clearArchRegs() { actualTC->clearArchRegs(); } 364 365 // 366 // New accessors for new decoder. 367 // 368 uint64_t readIntReg(int reg_idx) 369 { return actualTC->readIntReg(reg_idx); } 370 371 FloatReg readFloatReg(int reg_idx, int width) 372 { return actualTC->readFloatReg(reg_idx, width); } 373 374 FloatReg readFloatReg(int reg_idx) 375 { return actualTC->readFloatReg(reg_idx); } 376 377 FloatRegBits readFloatRegBits(int reg_idx, int width) 378 { return actualTC->readFloatRegBits(reg_idx, width); } 379 380 FloatRegBits readFloatRegBits(int reg_idx) 381 { return actualTC->readFloatRegBits(reg_idx); } 382 383 void setIntReg(int reg_idx, uint64_t val) 384 { actualTC->setIntReg(reg_idx, val); } 385 386 void setFloatReg(int reg_idx, FloatReg val, int width) 387 { actualTC->setFloatReg(reg_idx, val, width); } 388 389 void setFloatReg(int reg_idx, FloatReg val) 390 { actualTC->setFloatReg(reg_idx, val); } 391 392 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 393 { actualTC->setFloatRegBits(reg_idx, val, width); } 394 395 void setFloatRegBits(int reg_idx, FloatRegBits val) 396 { actualTC->setFloatRegBits(reg_idx, val); } 397 398 uint64_t readPC() { return actualTC->readPC(); } 399 400 void setPC(uint64_t val) { actualTC->setPC(val); } 401 402 uint64_t readNextPC() { return actualTC->readNextPC(); } 403 404 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 405 406 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 407 408 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 409 410 uint64_t readMicroPC() { return actualTC->readMicroPC(); } 411 412 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 413 414 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 415 416 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 417 418 MiscReg readMiscRegNoEffect(int misc_reg) 419 { return actualTC->readMiscRegNoEffect(misc_reg); } 420 421 MiscReg readMiscReg(int misc_reg) 422 { return actualTC->readMiscReg(misc_reg); } 423 424 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 425 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 426 427 void setMiscReg(int misc_reg, const MiscReg &val) 428 { return actualTC->setMiscReg(misc_reg, val); } 429 430 unsigned readStCondFailures() 431 { return actualTC->readStCondFailures(); } 432 433 void setStCondFailures(unsigned sc_failures) 434 { actualTC->setStCondFailures(sc_failures); } 435 436 // @todo: Fix this! 437 bool misspeculating() { return actualTC->misspeculating(); } 438 439#if !FULL_SYSTEM 440 void syscall(int64_t callnum) 441 { actualTC->syscall(callnum); } 442 443 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 444#endif 445}; 446 447#endif 448