thread_context.hh revision 5712
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/regfile.hh"
35#include "arch/types.hh"
36#include "config/full_system.hh"
37#include "mem/request.hh"
38#include "sim/faults.hh"
39#include "sim/host.hh"
40#include "sim/serialize.hh"
41#include "sim/syscallreturn.hh"
42#include "sim/byteswap.hh"
43
44// @todo: Figure out a more architecture independent way to obtain the ITB and
45// DTB pointers.
46namespace TheISA
47{
48    class DTB;
49    class ITB;
50}
51class BaseCPU;
52class EndQuiesceEvent;
53class Event;
54class TranslatingPort;
55class FunctionalPort;
56class VirtualPort;
57class Process;
58class System;
59namespace TheISA {
60    namespace Kernel {
61        class Statistics;
62    };
63};
64
65/**
66 * ThreadContext is the external interface to all thread state for
67 * anything outside of the CPU. It provides all accessor methods to
68 * state that might be needed by external objects, ranging from
69 * register values to things such as kernel stats. It is an abstract
70 * base class; the CPU can create its own ThreadContext by either
71 * deriving from it, or using the templated ProxyThreadContext.
72 *
73 * The ThreadContext is slightly different than the ExecContext.  The
74 * ThreadContext provides access to an individual thread's state; an
75 * ExecContext provides ISA access to the CPU (meaning it is
76 * implicitly multithreaded on SMT systems).  Additionally the
77 * ThreadState is an abstract class that exactly defines the
78 * interface; the ExecContext is a more implicit interface that must
79 * be implemented so that the ISA can access whatever state it needs.
80 */
81class ThreadContext
82{
83  protected:
84    typedef TheISA::RegFile RegFile;
85    typedef TheISA::MachInst MachInst;
86    typedef TheISA::IntReg IntReg;
87    typedef TheISA::FloatReg FloatReg;
88    typedef TheISA::FloatRegBits FloatRegBits;
89    typedef TheISA::MiscRegFile MiscRegFile;
90    typedef TheISA::MiscReg MiscReg;
91  public:
92    enum Status
93    {
94        /// Initialized but not running yet.  All CPUs start in
95        /// this state, but most transition to Active on cycle 1.
96        /// In MP or SMT systems, non-primary contexts will stay
97        /// in this state until a thread is assigned to them.
98        Unallocated,
99
100        /// Running.  Instructions should be executed only when
101        /// the context is in this state.
102        Active,
103
104        /// Temporarily inactive.  Entered while waiting for
105        /// synchronization, etc.
106        Suspended,
107
108        /// Permanently shut down.  Entered when target executes
109        /// m5exit pseudo-instruction.  When all contexts enter
110        /// this state, the simulation will terminate.
111        Halted
112    };
113
114    virtual ~ThreadContext() { };
115
116    virtual BaseCPU *getCpuPtr() = 0;
117
118    virtual int cpuId() = 0;
119
120    virtual TheISA::ITB *getITBPtr() = 0;
121
122    virtual TheISA::DTB *getDTBPtr() = 0;
123
124#if FULL_SYSTEM
125    virtual System *getSystemPtr() = 0;
126
127    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
128
129    virtual FunctionalPort *getPhysPort() = 0;
130
131    virtual VirtualPort *getVirtPort() = 0;
132
133    virtual void connectMemPorts(ThreadContext *tc) = 0;
134#else
135    virtual TranslatingPort *getMemPort() = 0;
136
137    virtual Process *getProcessPtr() = 0;
138#endif
139
140    virtual Status status() const = 0;
141
142    virtual void setStatus(Status new_status) = 0;
143
144    /// Set the status to Active.  Optional delay indicates number of
145    /// cycles to wait before beginning execution.
146    virtual void activate(int delay = 1) = 0;
147
148    /// Set the status to Suspended.
149    virtual void suspend(int delay = 0) = 0;
150
151    /// Set the status to Unallocated.
152    virtual void deallocate(int delay = 0) = 0;
153
154    /// Set the status to Halted.
155    virtual void halt(int delay = 0) = 0;
156
157#if FULL_SYSTEM
158    virtual void dumpFuncProfile() = 0;
159#endif
160
161    virtual void takeOverFrom(ThreadContext *old_context) = 0;
162
163    virtual void regStats(const std::string &name) = 0;
164
165    virtual void serialize(std::ostream &os) = 0;
166    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
167
168#if FULL_SYSTEM
169    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
170
171    // Not necessarily the best location for these...
172    // Having an extra function just to read these is obnoxious
173    virtual Tick readLastActivate() = 0;
174    virtual Tick readLastSuspend() = 0;
175
176    virtual void profileClear() = 0;
177    virtual void profileSample() = 0;
178#endif
179
180    virtual int getThreadNum() = 0;
181
182    // Also somewhat obnoxious.  Really only used for the TLB fault.
183    // However, may be quite useful in SPARC.
184    virtual TheISA::MachInst getInst() = 0;
185
186    virtual void copyArchRegs(ThreadContext *tc) = 0;
187
188    virtual void clearArchRegs() = 0;
189
190    //
191    // New accessors for new decoder.
192    //
193    virtual uint64_t readIntReg(int reg_idx) = 0;
194
195    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
196
197    virtual FloatReg readFloatReg(int reg_idx) = 0;
198
199    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
200
201    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
202
203    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
204
205    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
206
207    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
208
209    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
210
211    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
212
213    virtual uint64_t readPC() = 0;
214
215    virtual void setPC(uint64_t val) = 0;
216
217    virtual uint64_t readNextPC() = 0;
218
219    virtual void setNextPC(uint64_t val) = 0;
220
221    virtual uint64_t readNextNPC() = 0;
222
223    virtual void setNextNPC(uint64_t val) = 0;
224
225    virtual uint64_t readMicroPC() = 0;
226
227    virtual void setMicroPC(uint64_t val) = 0;
228
229    virtual uint64_t readNextMicroPC() = 0;
230
231    virtual void setNextMicroPC(uint64_t val) = 0;
232
233    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
234
235    virtual MiscReg readMiscReg(int misc_reg) = 0;
236
237    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
238
239    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
240
241    virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
242
243    virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
244
245    // Also not necessarily the best location for these two.  Hopefully will go
246    // away once we decide upon where st cond failures goes.
247    virtual unsigned readStCondFailures() = 0;
248
249    virtual void setStCondFailures(unsigned sc_failures) = 0;
250
251    // Only really makes sense for old CPU model.  Still could be useful though.
252    virtual bool misspeculating() = 0;
253
254#if !FULL_SYSTEM
255    virtual IntReg getSyscallArg(int i) = 0;
256
257    // used to shift args for indirect syscall
258    virtual void setSyscallArg(int i, IntReg val) = 0;
259
260    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
261
262    // Same with st cond failures.
263    virtual Counter readFuncExeInst() = 0;
264
265    virtual void syscall(int64_t callnum) = 0;
266
267    // This function exits the thread context in the CPU and returns
268    // 1 if the CPU has no more active threads (meaning it's OK to exit);
269    // Used in syscall-emulation mode when a  thread calls the exit syscall.
270    virtual int exit() { return 1; };
271#endif
272
273    /** function to compare two thread contexts (for debugging) */
274    static void compare(ThreadContext *one, ThreadContext *two);
275};
276
277/**
278 * ProxyThreadContext class that provides a way to implement a
279 * ThreadContext without having to derive from it. ThreadContext is an
280 * abstract class, so anything that derives from it and uses its
281 * interface will pay the overhead of virtual function calls.  This
282 * class is created to enable a user-defined Thread object to be used
283 * wherever ThreadContexts are used, without paying the overhead of
284 * virtual function calls when it is used by itself.  See
285 * simple_thread.hh for an example of this.
286 */
287template <class TC>
288class ProxyThreadContext : public ThreadContext
289{
290  public:
291    ProxyThreadContext(TC *actual_tc)
292    { actualTC = actual_tc; }
293
294  private:
295    TC *actualTC;
296
297  public:
298
299    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
300
301    int cpuId() { return actualTC->cpuId(); }
302
303    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
304
305    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
306
307#if FULL_SYSTEM
308    System *getSystemPtr() { return actualTC->getSystemPtr(); }
309
310    TheISA::Kernel::Statistics *getKernelStats()
311    { return actualTC->getKernelStats(); }
312
313    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
314
315    VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
316
317    void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
318#else
319    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
320
321    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
322#endif
323
324    Status status() const { return actualTC->status(); }
325
326    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
327
328    /// Set the status to Active.  Optional delay indicates number of
329    /// cycles to wait before beginning execution.
330    void activate(int delay = 1) { actualTC->activate(delay); }
331
332    /// Set the status to Suspended.
333    void suspend(int delay = 0) { actualTC->suspend(); }
334
335    /// Set the status to Unallocated.
336    void deallocate(int delay = 0) { actualTC->deallocate(); }
337
338    /// Set the status to Halted.
339    void halt(int delay = 0) { actualTC->halt(); }
340
341#if FULL_SYSTEM
342    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
343#endif
344
345    void takeOverFrom(ThreadContext *oldContext)
346    { actualTC->takeOverFrom(oldContext); }
347
348    void regStats(const std::string &name) { actualTC->regStats(name); }
349
350    void serialize(std::ostream &os) { actualTC->serialize(os); }
351    void unserialize(Checkpoint *cp, const std::string &section)
352    { actualTC->unserialize(cp, section); }
353
354#if FULL_SYSTEM
355    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
356
357    Tick readLastActivate() { return actualTC->readLastActivate(); }
358    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
359
360    void profileClear() { return actualTC->profileClear(); }
361    void profileSample() { return actualTC->profileSample(); }
362#endif
363
364    int getThreadNum() { return actualTC->getThreadNum(); }
365
366    // @todo: Do I need this?
367    MachInst getInst() { return actualTC->getInst(); }
368
369    // @todo: Do I need this?
370    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
371
372    void clearArchRegs() { actualTC->clearArchRegs(); }
373
374    //
375    // New accessors for new decoder.
376    //
377    uint64_t readIntReg(int reg_idx)
378    { return actualTC->readIntReg(reg_idx); }
379
380    FloatReg readFloatReg(int reg_idx, int width)
381    { return actualTC->readFloatReg(reg_idx, width); }
382
383    FloatReg readFloatReg(int reg_idx)
384    { return actualTC->readFloatReg(reg_idx); }
385
386    FloatRegBits readFloatRegBits(int reg_idx, int width)
387    { return actualTC->readFloatRegBits(reg_idx, width); }
388
389    FloatRegBits readFloatRegBits(int reg_idx)
390    { return actualTC->readFloatRegBits(reg_idx); }
391
392    void setIntReg(int reg_idx, uint64_t val)
393    { actualTC->setIntReg(reg_idx, val); }
394
395    void setFloatReg(int reg_idx, FloatReg val, int width)
396    { actualTC->setFloatReg(reg_idx, val, width); }
397
398    void setFloatReg(int reg_idx, FloatReg val)
399    { actualTC->setFloatReg(reg_idx, val); }
400
401    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
402    { actualTC->setFloatRegBits(reg_idx, val, width); }
403
404    void setFloatRegBits(int reg_idx, FloatRegBits val)
405    { actualTC->setFloatRegBits(reg_idx, val); }
406
407    uint64_t readPC() { return actualTC->readPC(); }
408
409    void setPC(uint64_t val) { actualTC->setPC(val); }
410
411    uint64_t readNextPC() { return actualTC->readNextPC(); }
412
413    void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
414
415    uint64_t readNextNPC() { return actualTC->readNextNPC(); }
416
417    void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
418
419    uint64_t readMicroPC() { return actualTC->readMicroPC(); }
420
421    void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
422
423    uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
424
425    void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
426
427    MiscReg readMiscRegNoEffect(int misc_reg)
428    { return actualTC->readMiscRegNoEffect(misc_reg); }
429
430    MiscReg readMiscReg(int misc_reg)
431    { return actualTC->readMiscReg(misc_reg); }
432
433    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
434    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
435
436    void setMiscReg(int misc_reg, const MiscReg &val)
437    { return actualTC->setMiscReg(misc_reg, val); }
438
439    unsigned readStCondFailures()
440    { return actualTC->readStCondFailures(); }
441
442    void setStCondFailures(unsigned sc_failures)
443    { actualTC->setStCondFailures(sc_failures); }
444
445    // @todo: Fix this!
446    bool misspeculating() { return actualTC->misspeculating(); }
447
448#if !FULL_SYSTEM
449    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
450
451    // used to shift args for indirect syscall
452    void setSyscallArg(int i, IntReg val)
453    { actualTC->setSyscallArg(i, val); }
454
455    void setSyscallReturn(SyscallReturn return_value)
456    { actualTC->setSyscallReturn(return_value); }
457
458    void syscall(int64_t callnum)
459    { actualTC->syscall(callnum); }
460
461    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
462#endif
463};
464
465#endif
466