thread_context.hh revision 3548
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/regfile.hh"
35#include "arch/syscallreturn.hh"
36#include "arch/types.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "sim/faults.hh"
40#include "sim/host.hh"
41#include "sim/serialize.hh"
42#include "sim/byteswap.hh"
43
44// @todo: Figure out a more architecture independent way to obtain the ITB and
45// DTB pointers.
46namespace TheISA
47{
48    class DTB;
49    class ITB;
50}
51class BaseCPU;
52class EndQuiesceEvent;
53class Event;
54class TranslatingPort;
55class FunctionalPort;
56class VirtualPort;
57class Process;
58class System;
59namespace TheISA {
60    namespace Kernel {
61        class Statistics;
62    };
63};
64
65/**
66 * ThreadContext is the external interface to all thread state for
67 * anything outside of the CPU. It provides all accessor methods to
68 * state that might be needed by external objects, ranging from
69 * register values to things such as kernel stats. It is an abstract
70 * base class; the CPU can create its own ThreadContext by either
71 * deriving from it, or using the templated ProxyThreadContext.
72 *
73 * The ThreadContext is slightly different than the ExecContext.  The
74 * ThreadContext provides access to an individual thread's state; an
75 * ExecContext provides ISA access to the CPU (meaning it is
76 * implicitly multithreaded on SMT systems).  Additionally the
77 * ThreadState is an abstract class that exactly defines the
78 * interface; the ExecContext is a more implicit interface that must
79 * be implemented so that the ISA can access whatever state it needs.
80 */
81class ThreadContext
82{
83  protected:
84    typedef TheISA::RegFile RegFile;
85    typedef TheISA::MachInst MachInst;
86    typedef TheISA::IntReg IntReg;
87    typedef TheISA::FloatReg FloatReg;
88    typedef TheISA::FloatRegBits FloatRegBits;
89    typedef TheISA::MiscRegFile MiscRegFile;
90    typedef TheISA::MiscReg MiscReg;
91  public:
92    enum Status
93    {
94        /// Initialized but not running yet.  All CPUs start in
95        /// this state, but most transition to Active on cycle 1.
96        /// In MP or SMT systems, non-primary contexts will stay
97        /// in this state until a thread is assigned to them.
98        Unallocated,
99
100        /// Running.  Instructions should be executed only when
101        /// the context is in this state.
102        Active,
103
104        /// Temporarily inactive.  Entered while waiting for
105        /// synchronization, etc.
106        Suspended,
107
108        /// Permanently shut down.  Entered when target executes
109        /// m5exit pseudo-instruction.  When all contexts enter
110        /// this state, the simulation will terminate.
111        Halted
112    };
113
114    virtual ~ThreadContext() { };
115
116    virtual BaseCPU *getCpuPtr() = 0;
117
118    virtual void setCpuId(int id) = 0;
119
120    virtual int readCpuId() = 0;
121
122#if FULL_SYSTEM
123    virtual System *getSystemPtr() = 0;
124
125    virtual TheISA::ITB *getITBPtr() = 0;
126
127    virtual TheISA::DTB *getDTBPtr() = 0;
128
129    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
130
131    virtual FunctionalPort *getPhysPort() = 0;
132
133    virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
134
135    virtual void delVirtPort(VirtualPort *vp) = 0;
136#else
137    virtual TranslatingPort *getMemPort() = 0;
138
139    virtual Process *getProcessPtr() = 0;
140#endif
141
142    virtual Status status() const = 0;
143
144    virtual void setStatus(Status new_status) = 0;
145
146    /// Set the status to Active.  Optional delay indicates number of
147    /// cycles to wait before beginning execution.
148    virtual void activate(int delay = 1) = 0;
149
150    /// Set the status to Suspended.
151    virtual void suspend() = 0;
152
153    /// Set the status to Unallocated.
154    virtual void deallocate(int delay = 0) = 0;
155
156    /// Set the status to Halted.
157    virtual void halt() = 0;
158
159#if FULL_SYSTEM
160    virtual void dumpFuncProfile() = 0;
161#endif
162
163    virtual void takeOverFrom(ThreadContext *old_context) = 0;
164
165    virtual void regStats(const std::string &name) = 0;
166
167    virtual void serialize(std::ostream &os) = 0;
168    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
169
170#if FULL_SYSTEM
171    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
172
173    // Not necessarily the best location for these...
174    // Having an extra function just to read these is obnoxious
175    virtual Tick readLastActivate() = 0;
176    virtual Tick readLastSuspend() = 0;
177
178    virtual void profileClear() = 0;
179    virtual void profileSample() = 0;
180#endif
181
182    virtual int getThreadNum() = 0;
183
184    // Also somewhat obnoxious.  Really only used for the TLB fault.
185    // However, may be quite useful in SPARC.
186    virtual TheISA::MachInst getInst() = 0;
187
188    virtual void copyArchRegs(ThreadContext *tc) = 0;
189
190    virtual void clearArchRegs() = 0;
191
192    //
193    // New accessors for new decoder.
194    //
195    virtual uint64_t readIntReg(int reg_idx) = 0;
196
197    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
198
199    virtual FloatReg readFloatReg(int reg_idx) = 0;
200
201    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
202
203    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
204
205    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
206
207    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
208
209    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
210
211    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
212
213    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
214
215    virtual uint64_t readPC() = 0;
216
217    virtual void setPC(uint64_t val) = 0;
218
219    virtual uint64_t readNextPC() = 0;
220
221    virtual void setNextPC(uint64_t val) = 0;
222
223    virtual uint64_t readNextNPC() = 0;
224
225    virtual void setNextNPC(uint64_t val) = 0;
226
227    virtual MiscReg readMiscReg(int misc_reg) = 0;
228
229    virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
230
231    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
232
233    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
234
235    // Also not necessarily the best location for these two.  Hopefully will go
236    // away once we decide upon where st cond failures goes.
237    virtual unsigned readStCondFailures() = 0;
238
239    virtual void setStCondFailures(unsigned sc_failures) = 0;
240
241    // Only really makes sense for old CPU model.  Still could be useful though.
242    virtual bool misspeculating() = 0;
243
244#if !FULL_SYSTEM
245    virtual IntReg getSyscallArg(int i) = 0;
246
247    // used to shift args for indirect syscall
248    virtual void setSyscallArg(int i, IntReg val) = 0;
249
250    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
251
252    // Same with st cond failures.
253    virtual Counter readFuncExeInst() = 0;
254
255    // This function exits the thread context in the CPU and returns
256    // 1 if the CPU has no more active threads (meaning it's OK to exit);
257    // Used in syscall-emulation mode when a  thread calls the exit syscall.
258    virtual int exit() { return 1; };
259#endif
260
261    virtual void changeRegFileContext(TheISA::RegContextParam param,
262            TheISA::RegContextVal val) = 0;
263};
264
265/**
266 * ProxyThreadContext class that provides a way to implement a
267 * ThreadContext without having to derive from it. ThreadContext is an
268 * abstract class, so anything that derives from it and uses its
269 * interface will pay the overhead of virtual function calls.  This
270 * class is created to enable a user-defined Thread object to be used
271 * wherever ThreadContexts are used, without paying the overhead of
272 * virtual function calls when it is used by itself.  See
273 * simple_thread.hh for an example of this.
274 */
275template <class TC>
276class ProxyThreadContext : public ThreadContext
277{
278  public:
279    ProxyThreadContext(TC *actual_tc)
280    { actualTC = actual_tc; }
281
282  private:
283    TC *actualTC;
284
285  public:
286
287    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
288
289    void setCpuId(int id) { actualTC->setCpuId(id); }
290
291    int readCpuId() { return actualTC->readCpuId(); }
292
293#if FULL_SYSTEM
294    System *getSystemPtr() { return actualTC->getSystemPtr(); }
295
296    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
297
298    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
299
300    TheISA::Kernel::Statistics *getKernelStats()
301    { return actualTC->getKernelStats(); }
302
303    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
304
305    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
306
307    void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
308#else
309    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
310
311    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
312#endif
313
314    Status status() const { return actualTC->status(); }
315
316    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
317
318    /// Set the status to Active.  Optional delay indicates number of
319    /// cycles to wait before beginning execution.
320    void activate(int delay = 1) { actualTC->activate(delay); }
321
322    /// Set the status to Suspended.
323    void suspend() { actualTC->suspend(); }
324
325    /// Set the status to Unallocated.
326    void deallocate(int delay = 0) { actualTC->deallocate(); }
327
328    /// Set the status to Halted.
329    void halt() { actualTC->halt(); }
330
331#if FULL_SYSTEM
332    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
333#endif
334
335    void takeOverFrom(ThreadContext *oldContext)
336    { actualTC->takeOverFrom(oldContext); }
337
338    void regStats(const std::string &name) { actualTC->regStats(name); }
339
340    void serialize(std::ostream &os) { actualTC->serialize(os); }
341    void unserialize(Checkpoint *cp, const std::string &section)
342    { actualTC->unserialize(cp, section); }
343
344#if FULL_SYSTEM
345    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
346
347    Tick readLastActivate() { return actualTC->readLastActivate(); }
348    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
349
350    void profileClear() { return actualTC->profileClear(); }
351    void profileSample() { return actualTC->profileSample(); }
352#endif
353
354    int getThreadNum() { return actualTC->getThreadNum(); }
355
356    // @todo: Do I need this?
357    MachInst getInst() { return actualTC->getInst(); }
358
359    // @todo: Do I need this?
360    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
361
362    void clearArchRegs() { actualTC->clearArchRegs(); }
363
364    //
365    // New accessors for new decoder.
366    //
367    uint64_t readIntReg(int reg_idx)
368    { return actualTC->readIntReg(reg_idx); }
369
370    FloatReg readFloatReg(int reg_idx, int width)
371    { return actualTC->readFloatReg(reg_idx, width); }
372
373    FloatReg readFloatReg(int reg_idx)
374    { return actualTC->readFloatReg(reg_idx); }
375
376    FloatRegBits readFloatRegBits(int reg_idx, int width)
377    { return actualTC->readFloatRegBits(reg_idx, width); }
378
379    FloatRegBits readFloatRegBits(int reg_idx)
380    { return actualTC->readFloatRegBits(reg_idx); }
381
382    void setIntReg(int reg_idx, uint64_t val)
383    { actualTC->setIntReg(reg_idx, val); }
384
385    void setFloatReg(int reg_idx, FloatReg val, int width)
386    { actualTC->setFloatReg(reg_idx, val, width); }
387
388    void setFloatReg(int reg_idx, FloatReg val)
389    { actualTC->setFloatReg(reg_idx, val); }
390
391    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
392    { actualTC->setFloatRegBits(reg_idx, val, width); }
393
394    void setFloatRegBits(int reg_idx, FloatRegBits val)
395    { actualTC->setFloatRegBits(reg_idx, val); }
396
397    uint64_t readPC() { return actualTC->readPC(); }
398
399    void setPC(uint64_t val) { actualTC->setPC(val); }
400
401    uint64_t readNextPC() { return actualTC->readNextPC(); }
402
403    void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
404
405    uint64_t readNextNPC() { return actualTC->readNextNPC(); }
406
407    void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
408
409    MiscReg readMiscReg(int misc_reg)
410    { return actualTC->readMiscReg(misc_reg); }
411
412    MiscReg readMiscRegWithEffect(int misc_reg)
413    { return actualTC->readMiscRegWithEffect(misc_reg); }
414
415    void setMiscReg(int misc_reg, const MiscReg &val)
416    { return actualTC->setMiscReg(misc_reg, val); }
417
418    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
419    { return actualTC->setMiscRegWithEffect(misc_reg, val); }
420
421    unsigned readStCondFailures()
422    { return actualTC->readStCondFailures(); }
423
424    void setStCondFailures(unsigned sc_failures)
425    { actualTC->setStCondFailures(sc_failures); }
426
427    // @todo: Fix this!
428    bool misspeculating() { return actualTC->misspeculating(); }
429
430#if !FULL_SYSTEM
431    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
432
433    // used to shift args for indirect syscall
434    void setSyscallArg(int i, IntReg val)
435    { actualTC->setSyscallArg(i, val); }
436
437    void setSyscallReturn(SyscallReturn return_value)
438    { actualTC->setSyscallReturn(return_value); }
439
440    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
441#endif
442
443    void changeRegFileContext(TheISA::RegContextParam param,
444            TheISA::RegContextVal val)
445    {
446        actualTC->changeRegFileContext(param, val);
447    }
448};
449
450#endif
451