thread_context.hh revision 2875
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "config/full_system.hh" 35#include "mem/request.hh" 36#include "sim/faults.hh" 37#include "sim/host.hh" 38#include "sim/serialize.hh" 39#include "sim/byteswap.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43class AlphaDTB; 44class AlphaITB; 45class BaseCPU; 46class EndQuiesceEvent; 47class Event; 48class TranslatingPort; 49class FunctionalPort; 50class VirtualPort; 51class Process; 52class System; 53namespace Kernel { 54 class Statistics; 55}; 56 57/** 58 * ThreadContext is the external interface to all thread state for 59 * anything outside of the CPU. It provides all accessor methods to 60 * state that might be needed by external objects, ranging from 61 * register values to things such as kernel stats. It is an abstract 62 * base class; the CPU can create its own ThreadContext by either 63 * deriving from it, or using the templated ProxyThreadContext. 64 * 65 * The ThreadContext is slightly different than the ExecContext. The 66 * ThreadContext provides access to an individual thread's state; an 67 * ExecContext provides ISA access to the CPU (meaning it is 68 * implicitly multithreaded on SMT systems). Additionally the 69 * ThreadState is an abstract class that exactly defines the 70 * interface; the ExecContext is a more implicit interface that must 71 * be implemented so that the ISA can access whatever state it needs. 72 */ 73class ThreadContext 74{ 75 protected: 76 typedef TheISA::RegFile RegFile; 77 typedef TheISA::MachInst MachInst; 78 typedef TheISA::IntReg IntReg; 79 typedef TheISA::FloatReg FloatReg; 80 typedef TheISA::FloatRegBits FloatRegBits; 81 typedef TheISA::MiscRegFile MiscRegFile; 82 typedef TheISA::MiscReg MiscReg; 83 public: 84 enum Status 85 { 86 /// Initialized but not running yet. All CPUs start in 87 /// this state, but most transition to Active on cycle 1. 88 /// In MP or SMT systems, non-primary contexts will stay 89 /// in this state until a thread is assigned to them. 90 Unallocated, 91 92 /// Running. Instructions should be executed only when 93 /// the context is in this state. 94 Active, 95 96 /// Temporarily inactive. Entered while waiting for 97 /// synchronization, etc. 98 Suspended, 99 100 /// Permanently shut down. Entered when target executes 101 /// m5exit pseudo-instruction. When all contexts enter 102 /// this state, the simulation will terminate. 103 Halted 104 }; 105 106 virtual ~ThreadContext() { }; 107 108 virtual BaseCPU *getCpuPtr() = 0; 109 110 virtual void setCpuId(int id) = 0; 111 112 virtual int readCpuId() = 0; 113 114#if FULL_SYSTEM 115 virtual System *getSystemPtr() = 0; 116 117 virtual AlphaITB *getITBPtr() = 0; 118 119 virtual AlphaDTB * getDTBPtr() = 0; 120 121 virtual Kernel::Statistics *getKernelStats() = 0; 122 123 virtual FunctionalPort *getPhysPort() = 0; 124 125 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 126 127 virtual void delVirtPort(VirtualPort *vp) = 0; 128#else 129 virtual TranslatingPort *getMemPort() = 0; 130 131 virtual Process *getProcessPtr() = 0; 132#endif 133 134 virtual Status status() const = 0; 135 136 virtual void setStatus(Status new_status) = 0; 137 138 /// Set the status to Active. Optional delay indicates number of 139 /// cycles to wait before beginning execution. 140 virtual void activate(int delay = 1) = 0; 141 142 /// Set the status to Suspended. 143 virtual void suspend() = 0; 144 145 /// Set the status to Unallocated. 146 virtual void deallocate(int delay = 0) = 0; 147 148 /// Set the status to Halted. 149 virtual void halt() = 0; 150 151#if FULL_SYSTEM 152 virtual void dumpFuncProfile() = 0; 153#endif 154 155 virtual void takeOverFrom(ThreadContext *old_context) = 0; 156 157 virtual void regStats(const std::string &name) = 0; 158 159 virtual void serialize(std::ostream &os) = 0; 160 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 161 162#if FULL_SYSTEM 163 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 164 165 // Not necessarily the best location for these... 166 // Having an extra function just to read these is obnoxious 167 virtual Tick readLastActivate() = 0; 168 virtual Tick readLastSuspend() = 0; 169 170 virtual void profileClear() = 0; 171 virtual void profileSample() = 0; 172#endif 173 174 virtual int getThreadNum() = 0; 175 176 // Also somewhat obnoxious. Really only used for the TLB fault. 177 // However, may be quite useful in SPARC. 178 virtual TheISA::MachInst getInst() = 0; 179 180 virtual void copyArchRegs(ThreadContext *tc) = 0; 181 182 virtual void clearArchRegs() = 0; 183 184 // 185 // New accessors for new decoder. 186 // 187 virtual uint64_t readIntReg(int reg_idx) = 0; 188 189 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 190 191 virtual FloatReg readFloatReg(int reg_idx) = 0; 192 193 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 194 195 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 196 197 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 198 199 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 200 201 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 202 203 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 204 205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 206 207 virtual uint64_t readPC() = 0; 208 209 virtual void setPC(uint64_t val) = 0; 210 211 virtual uint64_t readNextPC() = 0; 212 213 virtual void setNextPC(uint64_t val) = 0; 214 215 virtual uint64_t readNextNPC() = 0; 216 217 virtual void setNextNPC(uint64_t val) = 0; 218 219 virtual MiscReg readMiscReg(int misc_reg) = 0; 220 221 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 222 223 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 224 225 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 226 227 // Also not necessarily the best location for these two. Hopefully will go 228 // away once we decide upon where st cond failures goes. 229 virtual unsigned readStCondFailures() = 0; 230 231 virtual void setStCondFailures(unsigned sc_failures) = 0; 232 233#if FULL_SYSTEM 234 virtual bool inPalMode() = 0; 235#endif 236 237 // Only really makes sense for old CPU model. Still could be useful though. 238 virtual bool misspeculating() = 0; 239 240#if !FULL_SYSTEM 241 virtual IntReg getSyscallArg(int i) = 0; 242 243 // used to shift args for indirect syscall 244 virtual void setSyscallArg(int i, IntReg val) = 0; 245 246 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 247 248 // Same with st cond failures. 249 virtual Counter readFuncExeInst() = 0; 250 251 // This function exits the thread context in the CPU and returns 252 // 1 if the CPU has no more active threads (meaning it's OK to exit); 253 // Used in syscall-emulation mode when a thread calls the exit syscall. 254 virtual int exit() { return 1; }; 255#endif 256 257 virtual void changeRegFileContext(RegFile::ContextParam param, 258 RegFile::ContextVal val) = 0; 259}; 260 261/** 262 * ProxyThreadContext class that provides a way to implement a 263 * ThreadContext without having to derive from it. ThreadContext is an 264 * abstract class, so anything that derives from it and uses its 265 * interface will pay the overhead of virtual function calls. This 266 * class is created to enable a user-defined Thread object to be used 267 * wherever ThreadContexts are used, without paying the overhead of 268 * virtual function calls when it is used by itself. See 269 * simple_thread.hh for an example of this. 270 */ 271template <class TC> 272class ProxyThreadContext : public ThreadContext 273{ 274 public: 275 ProxyThreadContext(TC *actual_tc) 276 { actualTC = actual_tc; } 277 278 private: 279 TC *actualTC; 280 281 public: 282 283 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 284 285 void setCpuId(int id) { actualTC->setCpuId(id); } 286 287 int readCpuId() { return actualTC->readCpuId(); } 288 289#if FULL_SYSTEM 290 System *getSystemPtr() { return actualTC->getSystemPtr(); } 291 292 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } 293 294 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } 295 296 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 297 298 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 299 300 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 301 302 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 303#else 304 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 305 306 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 307#endif 308 309 Status status() const { return actualTC->status(); } 310 311 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 312 313 /// Set the status to Active. Optional delay indicates number of 314 /// cycles to wait before beginning execution. 315 void activate(int delay = 1) { actualTC->activate(delay); } 316 317 /// Set the status to Suspended. 318 void suspend() { actualTC->suspend(); } 319 320 /// Set the status to Unallocated. 321 void deallocate(int delay = 0) { actualTC->deallocate(); } 322 323 /// Set the status to Halted. 324 void halt() { actualTC->halt(); } 325 326#if FULL_SYSTEM 327 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 328#endif 329 330 void takeOverFrom(ThreadContext *oldContext) 331 { actualTC->takeOverFrom(oldContext); } 332 333 void regStats(const std::string &name) { actualTC->regStats(name); } 334 335 void serialize(std::ostream &os) { actualTC->serialize(os); } 336 void unserialize(Checkpoint *cp, const std::string §ion) 337 { actualTC->unserialize(cp, section); } 338 339#if FULL_SYSTEM 340 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 341 342 Tick readLastActivate() { return actualTC->readLastActivate(); } 343 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 344 345 void profileClear() { return actualTC->profileClear(); } 346 void profileSample() { return actualTC->profileSample(); } 347#endif 348 349 int getThreadNum() { return actualTC->getThreadNum(); } 350 351 // @todo: Do I need this? 352 MachInst getInst() { return actualTC->getInst(); } 353 354 // @todo: Do I need this? 355 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 356 357 void clearArchRegs() { actualTC->clearArchRegs(); } 358 359 // 360 // New accessors for new decoder. 361 // 362 uint64_t readIntReg(int reg_idx) 363 { return actualTC->readIntReg(reg_idx); } 364 365 FloatReg readFloatReg(int reg_idx, int width) 366 { return actualTC->readFloatReg(reg_idx, width); } 367 368 FloatReg readFloatReg(int reg_idx) 369 { return actualTC->readFloatReg(reg_idx); } 370 371 FloatRegBits readFloatRegBits(int reg_idx, int width) 372 { return actualTC->readFloatRegBits(reg_idx, width); } 373 374 FloatRegBits readFloatRegBits(int reg_idx) 375 { return actualTC->readFloatRegBits(reg_idx); } 376 377 void setIntReg(int reg_idx, uint64_t val) 378 { actualTC->setIntReg(reg_idx, val); } 379 380 void setFloatReg(int reg_idx, FloatReg val, int width) 381 { actualTC->setFloatReg(reg_idx, val, width); } 382 383 void setFloatReg(int reg_idx, FloatReg val) 384 { actualTC->setFloatReg(reg_idx, val); } 385 386 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 387 { actualTC->setFloatRegBits(reg_idx, val, width); } 388 389 void setFloatRegBits(int reg_idx, FloatRegBits val) 390 { actualTC->setFloatRegBits(reg_idx, val); } 391 392 uint64_t readPC() { return actualTC->readPC(); } 393 394 void setPC(uint64_t val) { actualTC->setPC(val); } 395 396 uint64_t readNextPC() { return actualTC->readNextPC(); } 397 398 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 399 400 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 401 402 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 403 404 MiscReg readMiscReg(int misc_reg) 405 { return actualTC->readMiscReg(misc_reg); } 406 407 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 408 { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 409 410 Fault setMiscReg(int misc_reg, const MiscReg &val) 411 { return actualTC->setMiscReg(misc_reg, val); } 412 413 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 414 { return actualTC->setMiscRegWithEffect(misc_reg, val); } 415 416 unsigned readStCondFailures() 417 { return actualTC->readStCondFailures(); } 418 419 void setStCondFailures(unsigned sc_failures) 420 { actualTC->setStCondFailures(sc_failures); } 421#if FULL_SYSTEM 422 bool inPalMode() { return actualTC->inPalMode(); } 423#endif 424 425 // @todo: Fix this! 426 bool misspeculating() { return actualTC->misspeculating(); } 427 428#if !FULL_SYSTEM 429 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 430 431 // used to shift args for indirect syscall 432 void setSyscallArg(int i, IntReg val) 433 { actualTC->setSyscallArg(i, val); } 434 435 void setSyscallReturn(SyscallReturn return_value) 436 { actualTC->setSyscallReturn(return_value); } 437 438 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 439#endif 440 441 void changeRegFileContext(RegFile::ContextParam param, 442 RegFile::ContextVal val) 443 { 444 actualTC->changeRegFileContext(param, val); 445 } 446}; 447 448#endif 449